| Message ID | 1407143908-19196-2-git-send-email-daniel.vetter@ffwll.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Aug 04, 2014 at 11:18:28AM +0200, Daniel Vetter wrote: > Users often can't do anything about this since their vendors stopped > providing BIOS updates. Also we seem to be able to hack around it > with increased latency values, and thus far the only reports have > been for screens with really high resolutions. So tune it down to a > level where only developers can see it. > > Also drop some of the end-user fluff. > > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Both patches make sense to me so: Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 8 +++----- > 1 file changed, 3 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 4f879494e0c5..684dc5f60544 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5235,11 +5235,9 @@ static void gen6_check_mch_setup(struct drm_device *dev) > uint32_t tmp; > > tmp = I915_READ(MCH_SSKPD); > - if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { > - DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); > - DRM_INFO("This can cause pipe underruns and display issues.\n"); > - DRM_INFO("Please upgrade your BIOS to fix this.\n"); > - } > + if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) > + DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", > + tmp); > } > > static void gen6_init_clock_gating(struct drm_device *dev) > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
2014-08-04 12:03 GMT-03:00 Ville Syrjälä <ville.syrjala@linux.intel.com>: > On Mon, Aug 04, 2014 at 11:18:28AM +0200, Daniel Vetter wrote: >> Users often can't do anything about this since their vendors stopped >> providing BIOS updates. Also we seem to be able to hack around it >> with increased latency values, and thus far the only reports have >> been for screens with really high resolutions. So tune it down to a >> level where only developers can see it. >> >> Also drop some of the end-user fluff. >> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> > > Both patches make sense to me so: > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> I never really understood why we expect a specific value for a specific field of the SSKPD on SNB. Isn't this value based on a lot of different machine-dependent variables? On HSW this doesn't make sense at all (and we don't have this check there, so the code is already fine). > >> --- >> drivers/gpu/drm/i915/intel_pm.c | 8 +++----- >> 1 file changed, 3 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 4f879494e0c5..684dc5f60544 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -5235,11 +5235,9 @@ static void gen6_check_mch_setup(struct drm_device *dev) >> uint32_t tmp; >> >> tmp = I915_READ(MCH_SSKPD); >> - if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { >> - DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); >> - DRM_INFO("This can cause pipe underruns and display issues.\n"); >> - DRM_INFO("Please upgrade your BIOS to fix this.\n"); >> - } >> + if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) >> + DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", >> + tmp); >> } >> >> static void gen6_init_clock_gating(struct drm_device *dev) >> -- >> 2.0.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 4f879494e0c5..684dc5f60544 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5235,11 +5235,9 @@ static void gen6_check_mch_setup(struct drm_device *dev) uint32_t tmp; tmp = I915_READ(MCH_SSKPD); - if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { - DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); - DRM_INFO("This can cause pipe underruns and display issues.\n"); - DRM_INFO("Please upgrade your BIOS to fix this.\n"); - } + if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) + DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", + tmp); } static void gen6_init_clock_gating(struct drm_device *dev)
Users often can't do anything about this since their vendors stopped providing BIOS updates. Also we seem to be able to hack around it with increased latency values, and thus far the only reports have been for screens with really high resolutions. So tune it down to a level where only developers can see it. Also drop some of the end-user fluff. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/intel_pm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)