From patchwork Mon Aug 4 18:15:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 4674181 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 70FD09F375 for ; Tue, 5 Aug 2014 01:14:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 93BA52017D for ; Tue, 5 Aug 2014 01:14:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 121152013D for ; Tue, 5 Aug 2014 01:14:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7A436E14D; Mon, 4 Aug 2014 18:14:19 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 18C5D6E14D for ; Mon, 4 Aug 2014 18:14:19 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 04 Aug 2014 18:14:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,801,1400050800"; d="scan'208";a="583413776" Received: from di-604.jf.intel.com (HELO rdvivi-hillsboro.jf.intel.com) ([10.7.196.77]) by orsmga002.jf.intel.com with ESMTP; 04 Aug 2014 18:14:17 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Aug 2014 11:15:16 -0700 Message-Id: <1407176119-5294-4-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com> References: <1407176119-5294-1-git-send-email-rodrigo.vivi@intel.com> Cc: Rodrigo Vivi , Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 4/7] drm/i915/bdw: cs-stall before state cache invld w/a X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-3.3 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky We do this already for previous GENs. I guess we must do it for BDW too according to DOCS. "Pipe_control with CS-stall bit set must be issued before a pipe-control command that has the State Cache Invalidate bit set." This does not solve the problem I have unfortunately. I didn't check if this was in Ville's CHV series. If it was, I apologize. NOTE: I tried to use smaller lengths for the command, but nothing made it happy except 6. Cc: Kenneth Graunke Cc: Jordan Justen Signed-off-by: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 9a562b5..2e566e0 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -279,17 +279,25 @@ gen6_render_ring_flush(struct intel_engine_cs *ring, static int gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) { - int ret; + int ret, size = 4; - ret = intel_ring_begin(ring, 4); + if (IS_BROADWELL(ring->dev)) + size += 2; + + ret = intel_ring_begin(ring, size); if (ret) return ret; - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size)); intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD); intel_ring_emit(ring, 0); intel_ring_emit(ring, 0); + if (IS_BROADWELL(ring->dev)) { + intel_ring_emit(ring, 0); + intel_ring_emit(ring, 0); + } + intel_ring_advance(ring); return 0; @@ -422,6 +430,11 @@ gen8_render_ring_flush(struct intel_engine_cs *ring, flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; flags |= PIPE_CONTROL_QW_WRITE; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ + gen7_render_ring_cs_stall_wa(ring); } return gen8_emit_pipe_control(ring, flags, scratch_addr);