From patchwork Fri Aug 22 03:11:43 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 4760921 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7ECBAC033A for ; Fri, 22 Aug 2014 03:13:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 79410201BC for ; Fri, 22 Aug 2014 03:13:55 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0B513201BA for ; Fri, 22 Aug 2014 03:13:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0BEC6E87D; Thu, 21 Aug 2014 20:13:51 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id B7F826E866 for ; Thu, 21 Aug 2014 20:13:22 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 21 Aug 2014 20:05:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="375575820" Received: from unknown (HELO ironside.intel.com) ([10.255.12.192]) by FMSMGA003.fm.intel.com with ESMTP; 21 Aug 2014 20:09:12 -0700 From: Ben Widawsky To: Intel GFX Date: Thu, 21 Aug 2014 20:11:43 -0700 Message-Id: <1408677155-1840-21-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 2.0.4 In-Reply-To: <1408677155-1840-1-git-send-email-benjamin.widawsky@intel.com> References: <1408677155-1840-1-git-send-email-benjamin.widawsky@intel.com> Cc: Ben Widawsky , Ben Widawsky Subject: [Intel-gfx] [PATCH 20/68] drm/i915: Make pin global flags explicit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The driver currently lets callers pin global, and then tries to do things correctly inside the function. Doing so has two downsides: 1. It's not possible to exclusively pin to a global, or an aliasing address space. 2. It's difficult to read, and understand. The eventual goal when realized should fix both of the issues. This patch which should have no functional impact begins to address these issues without intentionally breaking things. v2: Replace PIN_GLOBAL with PIN_ALIASING in _pin(). Copy paste error v3: Rebased/reworked with flag conflict from negative relocations Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++------ drivers/gpu/drm/i915/i915_gem.c | 31 +++++++++++++++++++++++------- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 ++++++-- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++++++++++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 6 +++++- 5 files changed, 53 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d1750d5..0db17f8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2300,11 +2300,13 @@ void i915_init_vm(struct drm_i915_private *dev_priv, void i915_gem_free_object(struct drm_gem_object *obj); void i915_gem_vma_destroy(struct i915_vma *vma); -#define PIN_MAPPABLE 0x1 -#define PIN_NONBLOCK 0x2 -#define PIN_GLOBAL 0x4 -#define PIN_OFFSET_BIAS 0x8 -#define PIN_OFFSET_MASK (~4095) +#define PIN_MAPPABLE (1<<0) +#define PIN_NONBLOCK (1<<1) +#define PIN_GLOBAL (1<<2) +#define PIN_ALIASING (1<<3) +#define PIN_GLOBAL_ALIASED (PIN_ALIASING | PIN_GLOBAL) +#define PIN_OFFSET_BIAS (1<<4) +#define PIN_OFFSET_MASK (PAGE_MASK) int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, struct i915_address_space *vm, uint32_t alignment, @@ -2511,7 +2513,7 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, uint32_t alignment, unsigned flags) { - return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); + return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL_ALIASED); } static inline int diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 5f66939..1dd5f43 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3496,8 +3496,12 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, unsigned long end = flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; struct i915_vma *vma; + u32 vma_bind_flags = 0; int ret; + if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) + flags |= PIN_GLOBAL; + fence_size = i915_gem_get_gtt_size(dev, obj->base.size, obj->tiling_mode); @@ -3584,9 +3588,11 @@ search_free: WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); + if (flags & PIN_GLOBAL_ALIASED) + vma_bind_flags = GLOBAL_BIND | ALIASING_BIND; + trace_i915_vma_bind(vma, flags); - i915_gem_vma_bind(vma, obj->cache_level, - flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0); + i915_gem_vma_bind(vma, obj->cache_level, vma_bind_flags); i915_gem_verify_gtt(dev); return vma; @@ -3796,9 +3802,14 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, } list_for_each_entry(vma, &obj->vma_list, vma_link) - if (drm_mm_node_allocated(&vma->node)) - i915_gem_vma_bind(vma, cache_level, - obj->has_global_gtt_mapping ? GLOBAL_BIND : 0); + if (drm_mm_node_allocated(&vma->node)) { + u32 bind_flags = 0; + if (obj->has_global_gtt_mapping) + bind_flags |= GLOBAL_BIND; + if (obj->has_aliasing_ppgtt_mapping) + bind_flags |= ALIASING_BIND; + i915_gem_vma_bind(vma, cache_level, bind_flags); + } } list_for_each_entry(vma, &obj->vma_list, vma_link) @@ -4198,8 +4209,14 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj, return PTR_ERR(vma); } - if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) - i915_gem_vma_bind(vma, obj->cache_level, GLOBAL_BIND); + if (flags & PIN_GLOBAL_ALIASED) { + u32 bind_flags = 0; + if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping) + bind_flags |= GLOBAL_BIND; + if (flags & PIN_ALIASING && !obj->has_aliasing_ppgtt_mapping) + bind_flags |= ALIASING_BIND; + i915_gem_vma_bind(vma, obj->cache_level, bind_flags); + } vma->pin_count++; if (flags & PIN_MAPPABLE) diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 884ec39..0c7adb8 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -377,7 +377,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, list_first_entry(&target_i915_obj->vma_list, typeof(*vma), vma_link); i915_gem_vma_bind(vma, target_i915_obj->cache_level, - GLOBAL_BIND); + GLOBAL_BIND | ALIASING_BIND); } /* Validate that the target is in a valid r/w GPU domain */ @@ -564,6 +564,7 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, if (need_fence || need_reloc_mappable(vma)) flags |= PIN_MAPPABLE; + /* FIXME: What kind of bind does Chris want? */ if (entry->flags & EXEC_OBJECT_NEEDS_GTT) flags |= PIN_GLOBAL; if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) @@ -1393,7 +1394,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, * allocate space first */ struct i915_vma *vma = i915_gem_obj_to_ggtt(batch_obj); BUG_ON(!vma); - i915_gem_vma_bind(vma, batch_obj->cache_level, GLOBAL_BIND); + /* FIXME: Current secure dispatch code actually uses PPGTT. We + * need to fix this eventually */ + i915_gem_vma_bind(vma, batch_obj->cache_level, + GLOBAL_BIND | ALIASING_BIND); } if (flags & I915_DISPATCH_SECURE) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2a75bce..0fb24b5 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1342,8 +1342,16 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) * Unfortunately above, we've just wiped out the mappings * without telling our object about it. So we need to fake it. */ - obj->has_global_gtt_mapping = 0; - i915_gem_vma_bind(vma, obj->cache_level, GLOBAL_BIND); + if (obj->has_global_gtt_mapping || obj->has_aliasing_ppgtt_mapping) { + u32 bind_flags = 0; + if (obj->has_global_gtt_mapping) + bind_flags |= GLOBAL_BIND; + if (obj->has_aliasing_ppgtt_mapping) + bind_flags |= ALIASING_BIND; + obj->has_global_gtt_mapping = 0; + obj->has_aliasing_ppgtt_mapping = 0; + i915_gem_vma_bind(vma, obj->cache_level, bind_flags); + } } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 593b5d0..6785060 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -157,8 +157,12 @@ struct i915_vma { * setting the valid PTE entries to a reserved scratch page. */ void (*unbind_vma)(struct i915_vma *vma); /* Map an object into an address space with the given cache flags. */ + +/* Only use this if you know you want a strictly global binding */ #define GLOBAL_BIND (1<<0) -#define PTE_READ_ONLY (1<<1) +/* Only use this if you know you want a strictly aliased binding */ +#define ALIASING_BIND (1<<1) +#define PTE_READ_ONLY (1<<2) void (*bind_vma)(struct i915_vma *vma, enum i915_cache_level cache_level, u32 flags);