| Message ID | 1411563032-9476-3-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
I went through and compared this against both the spec (the state commands listed in 3D-Media-GPGPU chapter 3D Pipeline Stages section) and the other information I've seen on recommended setup, and as far as I can tell this looks good. It still might be worth getting another set of eyes on this, but it is Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com> On Wed, Sep 24, 2014 at 05:50:32AM -0700, Mika Kuoppala wrote: > From: Armin Reese <armin.c.reese@intel.com> > > Modifications to 'null_state_gen' so it can generate GEN9 > golden context batch buffer source for SKL. > > v2: - rebased on top of gen8 changes (Mika) > - fixed state base address command size (Mika) > - base address size macro as pages (Mika) > > Signed-off-by: Armin Reese <armin.c.reese@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > lib/gen9_render.h | 8 + > tools/null_state_gen/Makefile.am | 3 +- > tools/null_state_gen/intel_null_state_gen.c | 34 +- > tools/null_state_gen/intel_renderstate_gen9.c | 442 ++++++++++++++++++++++++++ > 4 files changed, 476 insertions(+), 11 deletions(-) > create mode 100644 lib/gen9_render.h > create mode 100644 tools/null_state_gen/intel_renderstate_gen9.c > > diff --git a/lib/gen9_render.h b/lib/gen9_render.h > new file mode 100644 > index 0000000..a061808 > --- /dev/null > +++ b/lib/gen9_render.h > @@ -0,0 +1,8 @@ > +#ifndef GEN9_RENDER_H > +#define GEN9_RENDER_H > + > +#include "gen8_render.h" > + > +#define GEN9_PIPELINE_SELECT (GEN6_3D(1, 1, 4) | (3 << 8)) > + > +#endif /* GEN9_RENDER_H */ > diff --git a/tools/null_state_gen/Makefile.am b/tools/null_state_gen/Makefile.am > index 58fbd53..b131e0d 100644 > --- a/tools/null_state_gen/Makefile.am > +++ b/tools/null_state_gen/Makefile.am > @@ -8,9 +8,10 @@ intel_null_state_gen_SOURCES = \ > intel_renderstate_gen6.c \ > intel_renderstate_gen7.c \ > intel_renderstate_gen8.c \ > + intel_renderstate_gen9.c \ > intel_null_state_gen.c > > -gens := 6 7 8 > +gens := 6 7 8 9 > > h = /tmp/intel_renderstate_gen$$gen.c > state_headers: intel_null_state_gen > diff --git a/tools/null_state_gen/intel_null_state_gen.c b/tools/null_state_gen/intel_null_state_gen.c > index a7eb22b..1021a37 100644 > --- a/tools/null_state_gen/intel_null_state_gen.c > +++ b/tools/null_state_gen/intel_null_state_gen.c > @@ -5,21 +5,23 @@ > > #include "intel_batchbuffer.h" > > -#define STATE_ALIGN 64 > - > extern int gen6_setup_null_render_state(struct intel_batchbuffer *batch); > extern int gen7_setup_null_render_state(struct intel_batchbuffer *batch); > extern int gen8_setup_null_render_state(struct intel_batchbuffer *batch); > +extern int gen9_setup_null_render_state(struct intel_batchbuffer *batch); > > static int debug = 0; > > static void print_usage(char *s) > { > fprintf(stderr, "%s: <gen>\n" > - " gen: gen to generate for (6,7,8)\n", > - s); > + " gen: gen to generate for (6,7,8,9)\n", > + s); > } > > +/* Creates the intel_renderstate_genX.c file for the particular > + * GEN product > + */ > static int print_state(int gen, struct intel_batchbuffer *batch) > { > int i; > @@ -29,24 +31,32 @@ static int print_state(int gen, struct intel_batchbuffer *batch) > > printf("#include \"intel_renderstate.h\"\n\n"); > > + /* Relocation offsets. These are byte offsets in the golden context > + * batch buffer where the BB graphics address will be added to > + * the indirect state offset already stored in those locations. The > + * resulting value will inform the GPU where the indirect states are. > + */ > printf("static const u32 gen%d_null_state_relocs[] = {\n", gen); > for (i = 0; i < batch->cmds->num_items; i++) { > if (intel_batch_is_reloc(batch, i)) > printf("\t0x%08x,\n", i * 4); > } > - printf("\t%d,\n", -1); > - printf("};\n\n"); > + printf("\t-1,\n};\n\n"); > > + /* GPU commands to execute to set up the RCS golden state. This > + * state will become the default config. > + */ > printf("static const u32 gen%d_null_state_batch[] = {\n", gen); > for (i = 0; i < intel_batch_num_cmds(batch); i++) { > + const int offset = i * 4; > const struct bb_item *cmd = intel_batch_cmd_get(batch, i); > printf("\t0x%08x,", cmd->data); > > if (debug) > - printf("\t /* 0x%08x %s '%s' */", i * 4, > - intel_batch_type_as_str(cmd), cmd->str); > + printf("\t /* 0x%08x %s '%s' */", offset, > + intel_batch_type_as_str(cmd), cmd->str); > > - if (i * 4 == batch->cmds_end_offset) { > + if (offset == batch->cmds_end_offset) { > cmds = i + 1; > printf("\t /* cmds end */"); > } > @@ -54,7 +64,7 @@ static int print_state(int gen, struct intel_batchbuffer *batch) > if (intel_batch_is_reloc(batch, i)) > printf("\t /* reloc */"); > > - if (i * 4 == batch->state_start_offset) > + if (offset == batch->state_start_offset) > printf("\t /* state start */"); > > if (i == intel_batch_num_cmds(batch) - 1) > @@ -73,6 +83,7 @@ static int print_state(int gen, struct intel_batchbuffer *batch) > return 0; > } > > +/* Selects generator function for the given product and executes it. */ > static int do_generate(int gen) > { > struct intel_batchbuffer *batch; > @@ -95,6 +106,9 @@ static int do_generate(int gen) > case 8: > null_state_gen = gen8_setup_null_render_state; > break; > + case 9: > + null_state_gen = gen9_setup_null_render_state; > + break; > } > > if (null_state_gen == NULL) { > diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c > new file mode 100644 > index 0000000..8956a58 > --- /dev/null > +++ b/tools/null_state_gen/intel_renderstate_gen9.c > @@ -0,0 +1,442 @@ > +#include <string.h> > +#include <stdio.h> > + > +#include "intel_batchbuffer.h" > +#include <lib/gen9_render.h> > +#include <lib/intel_reg.h> > + > +static void gen8_emit_wm(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2)); > + OUT_BATCH(GEN7_WM_LEGACY_DIAMOND_LINE_RASTERIZATION); > +} > + > +static void gen8_emit_ps(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2)); > + OUT_BATCH(0); > + OUT_BATCH(0); /* kernel hi */ > + OUT_BATCH(GEN7_PS_SPF_MODE); > + OUT_BATCH(0); /* scratch space stuff */ > + OUT_BATCH(0); /* scratch hi */ > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); // kernel 1 > + OUT_BATCH(0); /* kernel 1 hi */ > + OUT_BATCH(0); // kernel 2 > + OUT_BATCH(0); /* kernel 2 hi */ > +} > + > +static void gen8_emit_sf(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2)); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(1 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT | > + 1 << GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT | > + GEN7_SF_POINT_WIDTH_FROM_SOURCE | > + 8); > +} > + > +static void gen8_emit_vs(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN6_3DSTATE_VS | (9 - 2)); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(GEN7_VS_FLOATING_POINT_MODE_ALTERNATE); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > +} > + > +static void gen8_emit_hs(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN7_3DSTATE_HS | (9 - 2)); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT); > + OUT_BATCH(0); > +} > + > +static void gen8_emit_urb(struct intel_batchbuffer *batch) > +{ > + const int vs_entries = 64; > + const int vs_size = 2; > + const int vs_start = 4; > + > + OUT_BATCH(GEN7_3DSTATE_URB_VS); > + OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25)); > + > + OUT_BATCH(GEN7_3DSTATE_URB_HS); > + OUT_BATCH(0x0f << 25); > + > + OUT_BATCH(GEN7_3DSTATE_URB_DS); > + OUT_BATCH(0x0f << 25); > + > + OUT_BATCH(GEN7_3DSTATE_URB_GS); > + OUT_BATCH(0x0f << 25); > +} > + > +static void gen8_emit_vf_topology(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY); > + OUT_BATCH(_3DPRIM_TRILIST); > +} > + > +static void gen8_emit_so_decl_list(struct intel_batchbuffer *batch) > +{ > + const int num_decls = 128; > + int i; > + > + OUT_BATCH(GEN8_3DSTATE_SO_DECL_LIST | > + (((2 * num_decls) + 3) - 2) /* DWORD count - 2 */); > + OUT_BATCH(0); > + OUT_BATCH(num_decls); > + > + for (i = 0; i < num_decls; i++) { > + OUT_BATCH(0); > + OUT_BATCH(0); > + } > +} > + > +static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index) > +{ > + OUT_BATCH(GEN8_3DSTATE_SO_BUFFER | (8 - 2)); > + OUT_BATCH(index << 29); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > +} > + > +static void gen8_emit_chroma_key(struct intel_batchbuffer *batch, const int index) > +{ > + OUT_BATCH(GEN6_3DSTATE_CHROMA_KEY | (4 - 2)); > + OUT_BATCH(index << 30); > + OUT_BATCH(0); > + OUT_BATCH(0); > +} > + > +static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch) > +{ > + const int buffers = 33; > + int i; > + > + OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | > + (((4 * buffers) + 1)- 2) /* DWORD count - 2 */); > + > + for (i = 0; i < buffers; i++) { > + OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT | > + GEN7_VB0_BUFFER_ADDR_MOD_EN); > + OUT_BATCH(0); /* Address */ > + OUT_BATCH(0); > + OUT_BATCH(0); > + } > +} > + > +static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch) > +{ > + const int elements = 34; > + int i; > + > + OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | > + (((2 * elements) + 1) - 2) /* DWORD count - 2 */); > + > + /* Element 0 */ > + OUT_BATCH(VE0_VALID); > + OUT_BATCH( > + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | > + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | > + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | > + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); > + /* Elements 1 -> 33 */ > + for (i = 1; i < elements; i++) { > + OUT_BATCH(0); > + OUT_BATCH(0); > + } > +} > + > +static void gen8_emit_cc_state_pointers(struct intel_batchbuffer *batch) > +{ > + union { > + float fval; > + uint32_t uval; > + } u; > + > + unsigned offset; > + > + u.fval = 1.0f; > + > + offset = intel_batch_state_offset(batch, 64); > + OUT_STATE(0); > + OUT_STATE(0); /* Alpha reference value */ > + OUT_STATE(u.uval); /* Blend constant color RED */ > + OUT_STATE(u.uval); /* Blend constant color BLUE */ > + OUT_STATE(u.uval); /* Blend constant color GREEN */ > + OUT_STATE(u.uval); /* Blend constant color ALPHA */ > + > + OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS); > + OUT_BATCH_STATE_OFFSET(offset | 1); > +} > + > +static void gen8_emit_blend_state_pointers(struct intel_batchbuffer *batch) > +{ > + unsigned offset; > + int i; > + > + offset = intel_batch_state_offset(batch, 64); > + > + for (i = 0; i < 17; i++) > + OUT_STATE(0); > + > + OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); > + OUT_BATCH_STATE_OFFSET(offset | 1); > +} > + > +static void gen8_emit_ps_extra(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2)); > + OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID | > + GEN8_PSX_ATTRIBUTE_ENABLE); > + > +} > + > +static void gen8_emit_ps_blend(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2)); > + OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT); > +} > + > +static void gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer *batch) > +{ > + unsigned offset; > + > + offset = intel_batch_state_offset(batch, 32); > + > + OUT_STATE((uint32_t)0.0f); /* Minimum depth */ > + OUT_STATE((uint32_t)0.0f); /* Maximum depth */ > + > + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); > + OUT_BATCH_STATE_OFFSET(offset); > +} > + > +static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *batch) > +{ > + unsigned offset; > + int i; > + > + offset = intel_batch_state_offset(batch, 64); > + > + for (i = 0; i < 16; i++) > + OUT_STATE(0); > + > + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2)); > + OUT_BATCH_STATE_OFFSET(offset); > +} > + > +static void gen8_emit_primitive(struct intel_batchbuffer *batch) > +{ > + OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); > + OUT_BATCH(4); /* gen8+ ignore the topology type field */ > + OUT_BATCH(1); /* vertex count */ > + OUT_BATCH(0); > + OUT_BATCH(1); /* single instance */ > + OUT_BATCH(0); /* start instance location */ > + OUT_BATCH(0); /* index buffer offset, ignored */ > +} > + > +static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) { > + const unsigned offset = 0; > + OUT_BATCH(GEN6_STATE_BASE_ADDRESS | > + (19 - 2) /* DWORD count - 2 */); > + > + /* general state base address - requires BB address > + * added to state offset to be stored in this location > + */ > + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); > + OUT_BATCH(0); > + > + /* stateless data port */ > + OUT_BATCH(0); > + > + /* surface state base address - requires BB address > + * added to state offset to be stored in this location > + */ > + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); > + OUT_BATCH(0); > + > + /* dynamic state base address - requires BB address > + * added to state offset to be stored in this location > + */ > + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); > + OUT_BATCH(0); > + > + /* indirect state base address */ > + OUT_BATCH(BASE_ADDRESS_MODIFY); > + OUT_BATCH(0); > + > + /* instruction state base address - requires BB address > + * added to state offset to be stored in this location > + */ > + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); > + OUT_BATCH(0); > + > + /* general state buffer size */ > + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); > + /* dynamic state buffer size */ > + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); > + /* indirect object buffer size */ > + OUT_BATCH(0x0 | BUFFER_SIZE_MODIFY); > + /* intruction buffer size */ > + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); > + > + /* bindless surface state base address */ > + OUT_BATCH(0); > + OUT_BATCH(0); > + /* bindless surface state size */ > + OUT_BATCH(0); > +} > + > +/* > + * Generate the batch buffer commands needed to initialize the 3D engine > + * to its "golden state". > + */ > +int gen9_setup_null_render_state(struct intel_batchbuffer *batch) > +{ > + int ret; > + int i; > + > +#define GEN8_PIPE_CONTROL_GLOBAL_GTT (1 << 24) > + /* PIPE_CONTROL */ > + OUT_BATCH(GEN6_PIPE_CONTROL | > + (6 - 2)); /* DWORD count - 2 */ > + OUT_BATCH(GEN8_PIPE_CONTROL_GLOBAL_GTT); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + OUT_BATCH(0); > + > + /* PIPELINE_SELECT */ > + OUT_BATCH(GEN9_PIPELINE_SELECT | PIPELINE_SELECT_3D); > + > + gen8_emit_wm(batch); > + gen8_emit_ps(batch); > + gen8_emit_sf(batch); > + > + OUT_CMD(GEN7_3DSTATE_SBE, 6); /* Check w/ Gen8 code */ > + OUT_CMD(GEN8_3DSTATE_SBE_SWIZ, 11); > + > + gen8_emit_vs(batch); > + gen8_emit_hs(batch); > + > + OUT_CMD(GEN7_3DSTATE_GS, 10); > + OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5); > + OUT_CMD(GEN7_3DSTATE_DS, 11); /* Check w/ Gen8 code */ > + OUT_CMD(GEN6_3DSTATE_CLIP, 4); > + OUT_CMD(GEN7_3DSTATE_TE, 4); > + OUT_CMD(GEN8_3DSTATE_VF, 2); > + OUT_CMD(GEN8_3DSTATE_WM_HZ_OP, 5); > + > + /* URB States */ > + gen8_emit_urb(batch); > + > + OUT_CMD(GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC, 4); > + OUT_CMD(GEN8_3DSTATE_GATHER_POOL_ALLOC, 4); > + OUT_CMD(GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 4); > + > + /* Push Constants */ > + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2); > + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2); > + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2); > + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2); > + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2); > + > + /* Constants */ > + OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11); > + OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11); > + OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11); > + OUT_CMD(GEN7_3DSTATE_CONSTANT_GS, 11); > + OUT_CMD(GEN7_3DSTATE_CONSTANT_PS, 11); > + > + OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3); > + OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2); > + gen8_emit_vf_topology(batch); > + > + /* Streamer out declaration list */ > + gen8_emit_so_decl_list(batch); > + > + /* Streamer out buffers */ > + for (i = 0; i < 4; i++) { > + gen8_emit_so_buffer(batch, i); > + } > + > + /* State base addresses */ > + gen9_emit_state_base_address(batch); > + > + OUT_CMD(GEN6_STATE_SIP, 3); > + OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4); > + OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8); > + > + /* Chroma key */ > + for (i = 0; i < 4; i++) { > + gen8_emit_chroma_key(batch, i); > + } > + > + OUT_CMD(GEN6_3DSTATE_LINE_STIPPLE, 3); > + OUT_CMD(GEN6_3DSTATE_AA_LINE_PARAMS, 3); > + OUT_CMD(GEN7_3DSTATE_STENCIL_BUFFER, 5); > + OUT_CMD(GEN7_3DSTATE_HIER_DEPTH_BUFFER, 5); > + OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3); > + OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2); > + OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2); > + OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_OFFSET, 2); > + OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32); > + OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 1 + 16); > + OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 1 + 16); > + OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5); > + > + /* Vertex buffers */ > + gen8_emit_vertex_buffers(batch); > + gen8_emit_vertex_elements(batch); > + > + OUT_BATCH(GEN6_3DSTATE_VF_STATISTICS | 1 /* Enable */); > + > + gen8_emit_cc_state_pointers(batch); > + gen8_emit_blend_state_pointers(batch); > + gen8_emit_ps_extra(batch); > + gen8_emit_ps_blend(batch); > + > + /* 3D state sampler state pointers */ > + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2); > + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2); > + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2); > + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2); > + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2); > + > + OUT_CMD(GEN6_3DSTATE_SCISSOR_STATE_POINTERS, 2); > + > + gen8_emit_viewport_state_pointers_cc(batch); > + gen8_emit_viewport_state_pointers_sf_clip(batch); > + > + /* 3D state binding table pointers */ > + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, 2); > + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, 2); > + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, 2); > + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, 2); > + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, 2); > + > + /* Launch 3D operation */ > + gen8_emit_primitive(batch); > + > + OUT_BATCH(MI_BATCH_BUFFER_END); > + > + return ret; > +} > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/lib/gen9_render.h b/lib/gen9_render.h new file mode 100644 index 0000000..a061808 --- /dev/null +++ b/lib/gen9_render.h @@ -0,0 +1,8 @@ +#ifndef GEN9_RENDER_H +#define GEN9_RENDER_H + +#include "gen8_render.h" + +#define GEN9_PIPELINE_SELECT (GEN6_3D(1, 1, 4) | (3 << 8)) + +#endif /* GEN9_RENDER_H */ diff --git a/tools/null_state_gen/Makefile.am b/tools/null_state_gen/Makefile.am index 58fbd53..b131e0d 100644 --- a/tools/null_state_gen/Makefile.am +++ b/tools/null_state_gen/Makefile.am @@ -8,9 +8,10 @@ intel_null_state_gen_SOURCES = \ intel_renderstate_gen6.c \ intel_renderstate_gen7.c \ intel_renderstate_gen8.c \ + intel_renderstate_gen9.c \ intel_null_state_gen.c -gens := 6 7 8 +gens := 6 7 8 9 h = /tmp/intel_renderstate_gen$$gen.c state_headers: intel_null_state_gen diff --git a/tools/null_state_gen/intel_null_state_gen.c b/tools/null_state_gen/intel_null_state_gen.c index a7eb22b..1021a37 100644 --- a/tools/null_state_gen/intel_null_state_gen.c +++ b/tools/null_state_gen/intel_null_state_gen.c @@ -5,21 +5,23 @@ #include "intel_batchbuffer.h" -#define STATE_ALIGN 64 - extern int gen6_setup_null_render_state(struct intel_batchbuffer *batch); extern int gen7_setup_null_render_state(struct intel_batchbuffer *batch); extern int gen8_setup_null_render_state(struct intel_batchbuffer *batch); +extern int gen9_setup_null_render_state(struct intel_batchbuffer *batch); static int debug = 0; static void print_usage(char *s) { fprintf(stderr, "%s: <gen>\n" - " gen: gen to generate for (6,7,8)\n", - s); + " gen: gen to generate for (6,7,8,9)\n", + s); } +/* Creates the intel_renderstate_genX.c file for the particular + * GEN product + */ static int print_state(int gen, struct intel_batchbuffer *batch) { int i; @@ -29,24 +31,32 @@ static int print_state(int gen, struct intel_batchbuffer *batch) printf("#include \"intel_renderstate.h\"\n\n"); + /* Relocation offsets. These are byte offsets in the golden context + * batch buffer where the BB graphics address will be added to + * the indirect state offset already stored in those locations. The + * resulting value will inform the GPU where the indirect states are. + */ printf("static const u32 gen%d_null_state_relocs[] = {\n", gen); for (i = 0; i < batch->cmds->num_items; i++) { if (intel_batch_is_reloc(batch, i)) printf("\t0x%08x,\n", i * 4); } - printf("\t%d,\n", -1); - printf("};\n\n"); + printf("\t-1,\n};\n\n"); + /* GPU commands to execute to set up the RCS golden state. This + * state will become the default config. + */ printf("static const u32 gen%d_null_state_batch[] = {\n", gen); for (i = 0; i < intel_batch_num_cmds(batch); i++) { + const int offset = i * 4; const struct bb_item *cmd = intel_batch_cmd_get(batch, i); printf("\t0x%08x,", cmd->data); if (debug) - printf("\t /* 0x%08x %s '%s' */", i * 4, - intel_batch_type_as_str(cmd), cmd->str); + printf("\t /* 0x%08x %s '%s' */", offset, + intel_batch_type_as_str(cmd), cmd->str); - if (i * 4 == batch->cmds_end_offset) { + if (offset == batch->cmds_end_offset) { cmds = i + 1; printf("\t /* cmds end */"); } @@ -54,7 +64,7 @@ static int print_state(int gen, struct intel_batchbuffer *batch) if (intel_batch_is_reloc(batch, i)) printf("\t /* reloc */"); - if (i * 4 == batch->state_start_offset) + if (offset == batch->state_start_offset) printf("\t /* state start */"); if (i == intel_batch_num_cmds(batch) - 1) @@ -73,6 +83,7 @@ static int print_state(int gen, struct intel_batchbuffer *batch) return 0; } +/* Selects generator function for the given product and executes it. */ static int do_generate(int gen) { struct intel_batchbuffer *batch; @@ -95,6 +106,9 @@ static int do_generate(int gen) case 8: null_state_gen = gen8_setup_null_render_state; break; + case 9: + null_state_gen = gen9_setup_null_render_state; + break; } if (null_state_gen == NULL) { diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c new file mode 100644 index 0000000..8956a58 --- /dev/null +++ b/tools/null_state_gen/intel_renderstate_gen9.c @@ -0,0 +1,442 @@ +#include <string.h> +#include <stdio.h> + +#include "intel_batchbuffer.h" +#include <lib/gen9_render.h> +#include <lib/intel_reg.h> + +static void gen8_emit_wm(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN6_3DSTATE_WM | (2 - 2)); + OUT_BATCH(GEN7_WM_LEGACY_DIAMOND_LINE_RASTERIZATION); +} + +static void gen8_emit_ps(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN7_3DSTATE_PS | (12 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); /* kernel hi */ + OUT_BATCH(GEN7_PS_SPF_MODE); + OUT_BATCH(0); /* scratch space stuff */ + OUT_BATCH(0); /* scratch hi */ + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); // kernel 1 + OUT_BATCH(0); /* kernel 1 hi */ + OUT_BATCH(0); // kernel 2 + OUT_BATCH(0); /* kernel 2 hi */ +} + +static void gen8_emit_sf(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN6_3DSTATE_SF | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(1 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT | + 1 << GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT | + GEN7_SF_POINT_WIDTH_FROM_SOURCE | + 8); +} + +static void gen8_emit_vs(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN6_3DSTATE_VS | (9 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(GEN7_VS_FLOATING_POINT_MODE_ALTERNATE); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void gen8_emit_hs(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN7_3DSTATE_HS | (9 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT); + OUT_BATCH(0); +} + +static void gen8_emit_urb(struct intel_batchbuffer *batch) +{ + const int vs_entries = 64; + const int vs_size = 2; + const int vs_start = 4; + + OUT_BATCH(GEN7_3DSTATE_URB_VS); + OUT_BATCH(vs_entries | ((vs_size - 1) << 16) | (vs_start << 25)); + + OUT_BATCH(GEN7_3DSTATE_URB_HS); + OUT_BATCH(0x0f << 25); + + OUT_BATCH(GEN7_3DSTATE_URB_DS); + OUT_BATCH(0x0f << 25); + + OUT_BATCH(GEN7_3DSTATE_URB_GS); + OUT_BATCH(0x0f << 25); +} + +static void gen8_emit_vf_topology(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_3DSTATE_VF_TOPOLOGY); + OUT_BATCH(_3DPRIM_TRILIST); +} + +static void gen8_emit_so_decl_list(struct intel_batchbuffer *batch) +{ + const int num_decls = 128; + int i; + + OUT_BATCH(GEN8_3DSTATE_SO_DECL_LIST | + (((2 * num_decls) + 3) - 2) /* DWORD count - 2 */); + OUT_BATCH(0); + OUT_BATCH(num_decls); + + for (i = 0; i < num_decls; i++) { + OUT_BATCH(0); + OUT_BATCH(0); + } +} + +static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index) +{ + OUT_BATCH(GEN8_3DSTATE_SO_BUFFER | (8 - 2)); + OUT_BATCH(index << 29); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void gen8_emit_chroma_key(struct intel_batchbuffer *batch, const int index) +{ + OUT_BATCH(GEN6_3DSTATE_CHROMA_KEY | (4 - 2)); + OUT_BATCH(index << 30); + OUT_BATCH(0); + OUT_BATCH(0); +} + +static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch) +{ + const int buffers = 33; + int i; + + OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | + (((4 * buffers) + 1)- 2) /* DWORD count - 2 */); + + for (i = 0; i < buffers; i++) { + OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT | + GEN7_VB0_BUFFER_ADDR_MOD_EN); + OUT_BATCH(0); /* Address */ + OUT_BATCH(0); + OUT_BATCH(0); + } +} + +static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch) +{ + const int elements = 34; + int i; + + OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | + (((2 * elements) + 1) - 2) /* DWORD count - 2 */); + + /* Element 0 */ + OUT_BATCH(VE0_VALID); + OUT_BATCH( + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + /* Elements 1 -> 33 */ + for (i = 1; i < elements; i++) { + OUT_BATCH(0); + OUT_BATCH(0); + } +} + +static void gen8_emit_cc_state_pointers(struct intel_batchbuffer *batch) +{ + union { + float fval; + uint32_t uval; + } u; + + unsigned offset; + + u.fval = 1.0f; + + offset = intel_batch_state_offset(batch, 64); + OUT_STATE(0); + OUT_STATE(0); /* Alpha reference value */ + OUT_STATE(u.uval); /* Blend constant color RED */ + OUT_STATE(u.uval); /* Blend constant color BLUE */ + OUT_STATE(u.uval); /* Blend constant color GREEN */ + OUT_STATE(u.uval); /* Blend constant color ALPHA */ + + OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS); + OUT_BATCH_STATE_OFFSET(offset | 1); +} + +static void gen8_emit_blend_state_pointers(struct intel_batchbuffer *batch) +{ + unsigned offset; + int i; + + offset = intel_batch_state_offset(batch, 64); + + for (i = 0; i < 17; i++) + OUT_STATE(0); + + OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); + OUT_BATCH_STATE_OFFSET(offset | 1); +} + +static void gen8_emit_ps_extra(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_3DSTATE_PS_EXTRA | (2 - 2)); + OUT_BATCH(GEN8_PSX_PIXEL_SHADER_VALID | + GEN8_PSX_ATTRIBUTE_ENABLE); + +} + +static void gen8_emit_ps_blend(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN8_3DSTATE_PS_BLEND | (2 - 2)); + OUT_BATCH(GEN8_PS_BLEND_HAS_WRITEABLE_RT); +} + +static void gen8_emit_viewport_state_pointers_cc(struct intel_batchbuffer *batch) +{ + unsigned offset; + + offset = intel_batch_state_offset(batch, 32); + + OUT_STATE((uint32_t)0.0f); /* Minimum depth */ + OUT_STATE((uint32_t)0.0f); /* Maximum depth */ + + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); + OUT_BATCH_STATE_OFFSET(offset); +} + +static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *batch) +{ + unsigned offset; + int i; + + offset = intel_batch_state_offset(batch, 64); + + for (i = 0; i < 16; i++) + OUT_STATE(0); + + OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP | (2 - 2)); + OUT_BATCH_STATE_OFFSET(offset); +} + +static void gen8_emit_primitive(struct intel_batchbuffer *batch) +{ + OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); + OUT_BATCH(4); /* gen8+ ignore the topology type field */ + OUT_BATCH(1); /* vertex count */ + OUT_BATCH(0); + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); /* index buffer offset, ignored */ +} + +static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) { + const unsigned offset = 0; + OUT_BATCH(GEN6_STATE_BASE_ADDRESS | + (19 - 2) /* DWORD count - 2 */); + + /* general state base address - requires BB address + * added to state offset to be stored in this location + */ + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* stateless data port */ + OUT_BATCH(0); + + /* surface state base address - requires BB address + * added to state offset to be stored in this location + */ + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* dynamic state base address - requires BB address + * added to state offset to be stored in this location + */ + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* indirect state base address */ + OUT_BATCH(BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* instruction state base address - requires BB address + * added to state offset to be stored in this location + */ + OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); + OUT_BATCH(0); + + /* general state buffer size */ + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); + /* dynamic state buffer size */ + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); + /* indirect object buffer size */ + OUT_BATCH(0x0 | BUFFER_SIZE_MODIFY); + /* intruction buffer size */ + OUT_BATCH(GEN8_STATE_SIZE_PAGES(1) | BUFFER_SIZE_MODIFY); + + /* bindless surface state base address */ + OUT_BATCH(0); + OUT_BATCH(0); + /* bindless surface state size */ + OUT_BATCH(0); +} + +/* + * Generate the batch buffer commands needed to initialize the 3D engine + * to its "golden state". + */ +int gen9_setup_null_render_state(struct intel_batchbuffer *batch) +{ + int ret; + int i; + +#define GEN8_PIPE_CONTROL_GLOBAL_GTT (1 << 24) + /* PIPE_CONTROL */ + OUT_BATCH(GEN6_PIPE_CONTROL | + (6 - 2)); /* DWORD count - 2 */ + OUT_BATCH(GEN8_PIPE_CONTROL_GLOBAL_GTT); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + + /* PIPELINE_SELECT */ + OUT_BATCH(GEN9_PIPELINE_SELECT | PIPELINE_SELECT_3D); + + gen8_emit_wm(batch); + gen8_emit_ps(batch); + gen8_emit_sf(batch); + + OUT_CMD(GEN7_3DSTATE_SBE, 6); /* Check w/ Gen8 code */ + OUT_CMD(GEN8_3DSTATE_SBE_SWIZ, 11); + + gen8_emit_vs(batch); + gen8_emit_hs(batch); + + OUT_CMD(GEN7_3DSTATE_GS, 10); + OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5); + OUT_CMD(GEN7_3DSTATE_DS, 11); /* Check w/ Gen8 code */ + OUT_CMD(GEN6_3DSTATE_CLIP, 4); + OUT_CMD(GEN7_3DSTATE_TE, 4); + OUT_CMD(GEN8_3DSTATE_VF, 2); + OUT_CMD(GEN8_3DSTATE_WM_HZ_OP, 5); + + /* URB States */ + gen8_emit_urb(batch); + + OUT_CMD(GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC, 4); + OUT_CMD(GEN8_3DSTATE_GATHER_POOL_ALLOC, 4); + OUT_CMD(GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC, 4); + + /* Push Constants */ + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, 2); + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS, 2); + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS, 2); + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS, 2); + OUT_CMD(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS, 2); + + /* Constants */ + OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11); + OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11); + OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11); + OUT_CMD(GEN7_3DSTATE_CONSTANT_GS, 11); + OUT_CMD(GEN7_3DSTATE_CONSTANT_PS, 11); + + OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3); + OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2); + gen8_emit_vf_topology(batch); + + /* Streamer out declaration list */ + gen8_emit_so_decl_list(batch); + + /* Streamer out buffers */ + for (i = 0; i < 4; i++) { + gen8_emit_so_buffer(batch, i); + } + + /* State base addresses */ + gen9_emit_state_base_address(batch); + + OUT_CMD(GEN6_STATE_SIP, 3); + OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4); + OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8); + + /* Chroma key */ + for (i = 0; i < 4; i++) { + gen8_emit_chroma_key(batch, i); + } + + OUT_CMD(GEN6_3DSTATE_LINE_STIPPLE, 3); + OUT_CMD(GEN6_3DSTATE_AA_LINE_PARAMS, 3); + OUT_CMD(GEN7_3DSTATE_STENCIL_BUFFER, 5); + OUT_CMD(GEN7_3DSTATE_HIER_DEPTH_BUFFER, 5); + OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3); + OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2); + OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2); + OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_OFFSET, 2); + OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32); + OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 1 + 16); + OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 1 + 16); + OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5); + + /* Vertex buffers */ + gen8_emit_vertex_buffers(batch); + gen8_emit_vertex_elements(batch); + + OUT_BATCH(GEN6_3DSTATE_VF_STATISTICS | 1 /* Enable */); + + gen8_emit_cc_state_pointers(batch); + gen8_emit_blend_state_pointers(batch); + gen8_emit_ps_extra(batch); + gen8_emit_ps_blend(batch); + + /* 3D state sampler state pointers */ + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS, 2); + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS, 2); + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS, 2); + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS, 2); + OUT_CMD(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS, 2); + + OUT_CMD(GEN6_3DSTATE_SCISSOR_STATE_POINTERS, 2); + + gen8_emit_viewport_state_pointers_cc(batch); + gen8_emit_viewport_state_pointers_sf_clip(batch); + + /* 3D state binding table pointers */ + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS, 2); + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS, 2); + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS, 2); + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS, 2); + OUT_CMD(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS, 2); + + /* Launch 3D operation */ + gen8_emit_primitive(batch); + + OUT_BATCH(MI_BATCH_BUFFER_END); + + return ret; +}