From patchwork Thu Sep 25 17:03:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Taylor, Clinton A" X-Patchwork-Id: 4976641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A4D7BBEEA6 for ; Thu, 25 Sep 2014 17:05:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D9AC2024D for ; Thu, 25 Sep 2014 17:05:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 4325620295 for ; Thu, 25 Sep 2014 17:05:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4187E6E046; Thu, 25 Sep 2014 10:05:32 -0700 (PDT) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id F0F8E6E046 for ; Thu, 25 Sep 2014 10:05:30 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 25 Sep 2014 10:05:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,598,1406617200"; d="scan'208";a="605362268" Received: from cataylo2-ubuntu64-12.jf.intel.com ([134.134.145.123]) by fmsmga002.fm.intel.com with ESMTP; 25 Sep 2014 10:05:03 -0700 From: clinton.a.taylor@intel.com To: Intel-gfx@lists.freedesktop.org Date: Thu, 25 Sep 2014 10:03:53 -0700 Message-Id: <1411664633-7364-1-git-send-email-clinton.a.taylor@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1411495616-21883-1-git-send-email-clinton.a.taylor@intel.com> References: <1411495616-21883-1-git-send-email-clinton.a.taylor@intel.com> Cc: Daniel Vetter , Jani Nikula Subject: [Intel-gfx] [PATCH v3] drm/i915: Enable pixel replicated modes on BDW and HSW. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Clint Taylor Haswell and later silicon has added a new pixel replication register to the pipe timings for each transcoder. Now in addition to the DPLL_A_MD register for the pixel clock double, we also need to write to the TRANS_MULT_n (0x6002c) register to double the pixel data. Writing to the DPLL only double the pixel clock. ver2: Macro name change from MULTIPLY to PIPE_MULTI. (Daniel) ver3: Do not set pixel multiplier if transcoder is eDP (Ville) Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: Daniel Vetter Cc: Jani Nikula Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 10 +++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ad8179b..035d58c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2443,6 +2443,7 @@ enum punit_power_well { #define _PIPEASRC 0x6001c #define _BCLRPAT_A 0x60020 #define _VSYNCSHIFT_A 0x60028 +#define _MULTIPLY_A 0x6002c /* Pipe B timing regs */ #define _HTOTAL_B 0x61000 @@ -2454,6 +2455,7 @@ enum punit_power_well { #define _PIPEBSRC 0x6101c #define _BCLRPAT_B 0x61020 #define _VSYNCSHIFT_B 0x61028 +#define _MULTIPLY_B 0x6102c #define TRANSCODER_A_OFFSET 0x60000 #define TRANSCODER_B_OFFSET 0x61000 @@ -2474,6 +2476,7 @@ enum punit_power_well { #define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A) #define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A) #define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC) +#define PIPE_MULTI(trans) _TRANSCODER2(trans, _MULTIPLY_A) /* HSW+ eDP PSR registers */ #define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 858011d..f8c1f11 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4168,6 +4168,11 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) intel_set_pipe_timings(intel_crtc); + if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { + I915_WRITE(PIPE_MULTI(intel_crtc->config.cpu_transcoder), + intel_crtc->config.pixel_multiplier - 1); + } + if (intel_crtc->config.has_pch_encoder) { intel_cpu_transcoder_set_m_n(intel_crtc, &intel_crtc->config.fdi_m_n, NULL); @@ -7853,7 +7858,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && (I915_READ(IPS_CTL) & IPS_ENABLE); - pipe_config->pixel_multiplier = 1; + if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { + pipe_config->pixel_multiplier = + I915_READ(PIPE_MULTI(pipe_config->cpu_transcoder)) + 1; + } return true; }