From patchwork Tue Sep 30 10:05:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jike Song X-Patchwork-Id: 5001811 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 53D209F349 for ; Tue, 30 Sep 2014 10:11:41 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 60DFA201B4 for ; Tue, 30 Sep 2014 10:11:40 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 565EC2017D for ; Tue, 30 Sep 2014 10:11:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DADFA6E6C5; Tue, 30 Sep 2014 03:11:38 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id A6A7B6E6C5 for ; Tue, 30 Sep 2014 03:11:37 -0700 (PDT) Received: from azsmga001.ch.intel.com ([10.2.17.19]) by fmsmga103.fm.intel.com with ESMTP; 30 Sep 2014 03:02:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,625,1406617200"; d="scan'208";a="480959899" Received: from kvmgt.bj.intel.com ([10.238.154.64]) by azsmga001.ch.intel.com with ESMTP; 30 Sep 2014 03:11:35 -0700 From: Jike Song To: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org Date: Tue, 30 Sep 2014 18:05:34 +0800 Message-Id: <1412071538-19059-5-git-send-email-jike.song@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1412071538-19059-1-git-send-email-jike.song@intel.com> References: <1412071538-19059-1-git-send-email-jike.song@intel.com> Subject: [Intel-gfx] [RFC PATCH 4/8] drm/i915: redirect MMIO accesses to vgt if enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Jike Song --- drivers/gpu/drm/i915/i915_drv.h | 147 +++++++++++++++++++++++++++++++++--- drivers/gpu/drm/i915/intel_uncore.c | 3 + 2 files changed, 138 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c3b03f5..ed6f14e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -38,6 +38,7 @@ #include "intel_lrc.h" #include "i915_gem_gtt.h" #include "i915_gem_render_state.h" +#include "i915_vgt.h" #include #include #include @@ -2915,19 +2916,121 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); #define FORCEWAKE_MEDIA (1 << 1) #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) +#define I915_READ8(reg) \ +({ \ + u8 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u8), \ + false, true); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readb(dev_priv, \ + (reg), true); \ + __ret; \ +}) + +#define I915_READ16(reg) \ +({ \ + u16 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u16), \ + false, true); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readw(dev_priv, \ + (reg), true); \ + __ret; \ +}) + +#define I915_READ16_NOTRACE(reg) \ +({ \ + u16 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u16), \ + false, false); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readw(dev_priv, \ + (reg), false); \ + __ret; \ +}) + +#define I915_READ(reg) \ +({ \ + u32 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u32), \ + false, true); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readl(dev_priv, \ + (reg), true); \ + __ret; \ +}) + +#define I915_READ_NOTRACE(reg) \ +({ \ + u32 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u32), \ + false, false); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readl(dev_priv, \ + (reg), false); \ + __ret; \ +}) + -#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) -#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) +#define I915_WRITE8(reg, val) \ +({ \ + u8 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u8), \ + false, true); \ + else \ + dev_priv->uncore.funcs.mmio_writeb(dev_priv, \ + reg, val, true); \ +}) + +#define I915_WRITE16(reg, val) \ +({ \ + u16 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u16), \ + false, true); \ + else \ + dev_priv->uncore.funcs.mmio_writew(dev_priv, \ + reg, val, true); \ +}) + +#define I915_WRITE16_NOTRACE(reg, val) \ +({ \ + u16 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u16), \ + false, false); \ + else \ + dev_priv->uncore.funcs.mmio_writew(dev_priv, \ + reg, val, false); \ +}) -#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) -#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) -#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) -#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) +#define I915_WRITE(reg, val) \ +({ \ + u32 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u32), \ + false, true); \ + else \ + dev_priv->uncore.funcs.mmio_writel(dev_priv, \ + reg, val, true); \ +}) -#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) -#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) -#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) -#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) +#define I915_WRITE_NOTRACE(reg, val) \ +({ \ + u32 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u32), \ + false, false); \ + else \ + dev_priv->uncore.funcs.mmio_writel(dev_priv, \ + reg, val, false); \ +}) /* Be very careful with read/write 64-bit values. On 32-bit machines, they * will be implemented using 2 32-bit writes in an arbitrary order with @@ -2935,8 +3038,28 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); * act upon the intermediate value, possibly leading to corruption and * machine death. You have been warned. */ -#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) -#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) +#define I915_READ64(reg) \ +({ \ + u64 __ret = 0; \ + if (i915.enable_vgt) \ + vgt_emulate_host_read(reg, &__ret, sizeof(u64), \ + false, true); \ + else \ + __ret = dev_priv->uncore.funcs.mmio_readq(dev_priv, \ + (reg), true); \ + __ret; \ +}) + +#define I915_WRITE64(reg, val) \ +({ \ + u64 __val = (val); \ + if (i915.enable_vgt) \ + vgt_emulate_host_write(reg, &__val, sizeof(u64), \ + false, true); \ + else \ + dev_priv->uncore.funcs.mmio_writeq(dev_priv, \ + reg, val, true); \ +}) #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ u32 upper = I915_READ(upper_reg); \ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 0b0f4f8..774e0fa 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -948,6 +948,9 @@ void intel_uncore_init(struct drm_device *dev) dev_priv->uncore.funcs.mmio_readq = gen4_read64; break; } + + if (i915.enable_vgt) + i915_vgt_record_priv(dev_priv); } void intel_uncore_fini(struct drm_device *dev)