| Message ID | 1412089877-3998-1-git-send-email-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Rodrigo Vivi <rodrigo.vivi@intel.com> writes: > Program the default initial value of the L3SqcReg1 on BDW for performance > > v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out. > > Cc: Mika Kuoppala <mika.kuoppala@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 36a847a..33143cc 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4972,6 +4972,9 @@ enum punit_power_well { > #define GEN7_L3SQCREG1 0xB010 > #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 > > +#define GEN8_L3SQCREG1 0xB100 > +#define BDW_WA_L3SQCREG1_DEFAULT 0x00610000 > + This is the default value after reset. I have experimented with other values and nothing improves above noise level. Further, my suggestion to using 0x00810000 will cause a gpu hang...so there is dragons here. As you are writing the same default value that is already in register, and there is no indication that we should refresh anything, I would say this patch is not needed until someone comes along and shows something better than what the default is. Thanks, -Mika > #define GEN7_L3CNTLREG1 0xB01C > #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C > #define GEN7_L3AGDIS (1<<19) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 816a692..a37675d 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > * update the number of dwords required based on the > * actual number of workarounds applied > */ > - ret = intel_ring_begin(ring, 18); > + ret = intel_ring_begin(ring, 21); > if (ret) > return ret; > > @@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > intel_ring_emit_wa(ring, GEN7_GT_MODE, > GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); > > + /* WaProgramL3SqcReg1Default:bdw */ > + intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); > + > intel_ring_advance(ring); > > DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n", > -- > 1.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 36a847a..33143cc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4972,6 +4972,9 @@ enum punit_power_well { #define GEN7_L3SQCREG1 0xB010 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 +#define GEN8_L3SQCREG1 0xB100 +#define BDW_WA_L3SQCREG1_DEFAULT 0x00610000 + #define GEN7_L3CNTLREG1 0xB01C #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C #define GEN7_L3AGDIS (1<<19) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 816a692..a37675d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) * update the number of dwords required based on the * actual number of workarounds applied */ - ret = intel_ring_begin(ring, 18); + ret = intel_ring_begin(ring, 21); if (ret) return ret; @@ -751,6 +751,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) intel_ring_emit_wa(ring, GEN7_GT_MODE, GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); + /* WaProgramL3SqcReg1Default:bdw */ + intel_ring_emit_wa(ring, GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); + intel_ring_advance(ring); DRM_DEBUG_DRIVER("Number of Workarounds applied: %d\n",
Program the default initial value of the L3SqcReg1 on BDW for performance v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out. Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-)