From patchwork Mon Oct 20 13:17:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 5149861 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6EABAC11AC for ; Fri, 24 Oct 2014 21:28:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7EB7A20268 for ; Fri, 24 Oct 2014 21:28:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7E58820265 for ; Fri, 24 Oct 2014 21:28:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5C2E36EA35; Fri, 24 Oct 2014 14:24:46 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com [209.85.217.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A0BD6E088 for ; Mon, 20 Oct 2014 06:17:53 -0700 (PDT) Received: by mail-lb0-f171.google.com with SMTP id z12so3856484lbi.2 for ; Mon, 20 Oct 2014 06:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=ape140+NMKlHfR5IRM1HCoSWwpzsZuv56bPsyaeq6CA=; b=ul3DTv7uXnL5hTWgbK4s+XBJ4rZVJFfW6TkI2B4pFO+PEKuyZHUoPJ2pNS/HFjsRuC K4AZmyqVsHQty84Mp2ASGUXoamCp2t1rBmup25zfichteGcimiR5yOvxOLCD+MELMaAE i1rZXZJYldY4xP1IeuGqkgfpdYue5Okw6xSM+tgkLvjknpeEikfET3wPpxVloJa+O0Tv p9CHBM5BVzVK9T+ObfbKEpZUXn+jZ0uquk2JCIeNrOJO1DSJq36P1U8iwd5l8T/Hf/xl EPaGcq0DxCXrR15RpIzSCjFfRcqdAWYHWRsFIz3DXw93Bo53qO5d7R+MhDxwAV3+eIDI qzgg== X-Received: by 10.152.4.132 with SMTP id k4mr27419820lak.1.1413811072410; Mon, 20 Oct 2014 06:17:52 -0700 (PDT) Received: from snb-laptop.Elisa (a88-114-204-203.elisa-laajakaista.fi. [88.114.204.203]) by mx.google.com with ESMTPSA id h9sm3296533lae.44.2014.10.20.06.17.50 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 20 Oct 2014 06:17:51 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Mon, 20 Oct 2014 16:17:20 +0300 Message-Id: <1413811040-3308-1-git-send-email-conselvan2@gmail.com> X-Mailer: git-send-email 1.8.3.2 Cc: Ander Conselvan de Oliveira , ville.syrjala@intel.com, shuang.he@linux.intel.com Subject: [Intel-gfx] [PATCH] drm/i915: Use vblank evade mechanism in mmio_flip X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ander Conselvan de Oliveira Currently we program just DPSCNTR and DSPSTRIDE directly from the ring interrupt handler, which is fine since the hardware guarantees that those are update atomically. When we have atomic page flips we'll want to be able to update also the offset registers, and then we need to use the vblank evade mechanism to guarantee atomicity. Signed-off-by: Ander Conselvan de Oliveira Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_display.c | 21 ++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 5 ++++- drivers/gpu/drm/i915/intel_sprite.c | 4 ++-- 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6e6f150..6a234cf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9563,11 +9563,15 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) struct intel_framebuffer *intel_fb = to_intel_framebuffer(intel_crtc->base.primary->fb); struct drm_i915_gem_object *obj = intel_fb->obj; + bool atomic_update; + u32 start_vbl_count; u32 dspcntr; u32 reg; intel_mark_page_flip_active(intel_crtc); + atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); + reg = DSPCNTR(intel_crtc->plane); dspcntr = I915_READ(reg); @@ -9582,6 +9586,19 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) I915_WRITE(DSPSURF(intel_crtc->plane), intel_crtc->unpin_work->gtt_offset); POSTING_READ(DSPSURF(intel_crtc->plane)); + + if (atomic_update) + intel_pipe_update_end(intel_crtc, start_vbl_count); +} + +static void intel_mmio_flip_work_func(struct work_struct *work) +{ + struct intel_crtc *intel_crtc = + container_of(work, struct intel_crtc, mmio_flip.work); + + drm_modeset_lock(&intel_crtc->base.mutex, NULL); + intel_do_mmio_flip(intel_crtc); + drm_modeset_unlock(&intel_crtc->base.mutex); } static int intel_postpone_flip(struct drm_i915_gem_object *obj) @@ -9631,7 +9648,7 @@ void intel_notify_mmio_flip(struct intel_engine_cs *ring) continue; if (i915_seqno_passed(seqno, mmio_flip->seqno)) { - intel_do_mmio_flip(intel_crtc); + schedule_work(&intel_crtc->mmio_flip.work); mmio_flip->seqno = 0; ring->irq_put(ring); } @@ -9661,6 +9678,8 @@ static int intel_queue_mmio_flip(struct drm_device *dev, return 0; } + INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); + spin_lock_irq(&dev_priv->mmio_flip_lock); intel_crtc->mmio_flip.seqno = obj->last_write_seqno; intel_crtc->mmio_flip.ring_id = obj->ring->id; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5ab813c..5649776 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -400,6 +400,7 @@ struct intel_pipe_wm { struct intel_mmio_flip { u32 seqno; u32 ring_id; + struct work_struct work; }; struct intel_crtc { @@ -1158,7 +1159,9 @@ int intel_sprite_set_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); int intel_sprite_get_colorkey(struct drm_device *dev, void *data, struct drm_file *file_priv); - +bool intel_pipe_update_start(struct intel_crtc *crtc, + uint32_t *start_vbl_count); +void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count); /* intel_tv.c */ void intel_tv_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 2c060ad..3e7480a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -46,7 +46,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); } -static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) +bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) { struct drm_device *dev = crtc->base.dev; const struct drm_display_mode *mode = &crtc->config.adjusted_mode; @@ -112,7 +112,7 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl return true; } -static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) +void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) { struct drm_device *dev = crtc->base.dev; enum pipe pipe = crtc->pipe;