diff mbox

drm/i915: Emit even number of dwords when emitting LRIs

Message ID 1413968989-16840-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

arun.siluvery@linux.intel.com Oct. 22, 2014, 9:09 a.m. UTC
The number of DWords should be even when doing ring emits as
command sequences require QWord alignment.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Lespiau, Damien Oct. 22, 2014, 10:40 a.m. UTC | #1
On Wed, Oct 22, 2014 at 10:09:49AM +0100, Arun Siluvery wrote:
> The number of DWords should be even when doing ring emits as
> command sequences require QWord alignment.

It looks like we could just pad at the end of the batch instead of one
NOP per register write?

Also, It looks like we could use the LRI variant that can write more
than one register in one go (separate patch)?.
Lespiau, Damien Oct. 22, 2014, 10:54 a.m. UTC | #2
On Wed, Oct 22, 2014 at 11:40:30AM +0100, Damien Lespiau wrote:
> On Wed, Oct 22, 2014 at 10:09:49AM +0100, Arun Siluvery wrote:
> > The number of DWords should be even when doing ring emits as
> > command sequences require QWord alignment.
> 
> It looks like we could just pad at the end of the batch instead of one
> NOP per register write?
> 
> Also, It looks like we could use the LRI variant that can write more
> than one register in one go (separate patch)?.

Note that if you use the multi-register LRI variant, the number of
dwords will always be odd, so we'll always need to pad a NOP, that makes
it easy.
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 12a546f..79211ae 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -680,7 +680,7 @@  static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
 	if (ret)
 		return ret;
 
-	ret = intel_ring_begin(ring, w->count * 3);
+	ret = intel_ring_begin(ring, w->count * 4);
 	if (ret)
 		return ret;
 
@@ -688,6 +688,7 @@  static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 		intel_ring_emit(ring, w->reg[i].addr);
 		intel_ring_emit(ring, w->reg[i].value);
+		intel_ring_emit(ring, MI_NOOP);
 	}
 
 	intel_ring_advance(ring);