@@ -46,6 +46,11 @@ enum {
PINNED_LIST,
};
+enum {
+ LRC_CONTEXT_DUMP, /* First 1536 bytes of register state ctxt */
+ FULL_CONTEXT_DUMP, /* Full context (HW status + reg state ctxt */
+};
+
static const char *yesno(int v)
{
return v ? "yes" : "no";
@@ -119,6 +124,48 @@ static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
}
+/*
+ * Dump contents of GEM object to the screen. 8 DWORDs per line
+ */
+
+static void
+dump_32_obj(struct seq_file *m, struct drm_i915_gem_object *obj,
+ int start_pg, int num_pgs)
+{
+ struct page *page;
+ struct sg_page_iter sg_iter;
+ size_t pg_offset, obj_offset = 0;
+ uint32_t *pg_ptr, *curr_ptr;
+ int i, pg_cnt = 0;
+
+ for_each_sg_page(obj->pages->sgl, &sg_iter,
+ obj->pages->nents, start_pg) {
+ page = sg_page_iter_page(&sg_iter);
+
+ pg_ptr = (uint32_t *)kmap_atomic(page);
+ curr_ptr = pg_ptr;
+ pg_offset = 0;
+
+ while (pg_offset < PAGE_SIZE) {
+ seq_printf(m, "0x%08lx: ", obj_offset);
+ for (i = 0; i < 8; i++) {
+ seq_printf(m, "0x%08x ", *curr_ptr);
+ curr_ptr++;
+ }
+ seq_puts(m, "\n");
+
+ pg_offset += 8 * sizeof(uint32_t);
+ obj_offset += 8 * sizeof(uint32_t);
+ }
+
+ kunmap_atomic(pg_ptr);
+
+ if ((num_pgs != -1) &&
+ (++pg_cnt >= num_pgs))
+ break;
+ }
+}
+
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
@@ -1773,9 +1820,10 @@ static int i915_context_status(struct seq_file *m, void *unused)
return 0;
}
-static int i915_dump_lrc(struct seq_file *m, void *unused)
+static int i915_dump_lrc(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
+ uintptr_t dump_flag = (uintptr_t) node->info_ent->data;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_engine_cs *ring;
@@ -1795,24 +1843,40 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
for_each_ring(ring, dev_priv, i) {
struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
- if (ring->default_context == ctx)
+ if ((ring->default_context == ctx) &&
+ (dump_flag == LRC_CONTEXT_DUMP))
continue;
+ /*
+ * Hardware Status Page is in first page of context
+ * object. Register state context begins on second
+ * page.
+ */
if (ctx_obj) {
- struct page *page = i915_gem_object_get_page(ctx_obj, 1);
- uint32_t *reg_state = kmap_atomic(page);
- int j;
-
- seq_printf(m, "CONTEXT: %s %u\n", ring->name,
- intel_execlists_ctx_id(ctx_obj));
-
- for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
- seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
- i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
- reg_state[j], reg_state[j + 1],
- reg_state[j + 2], reg_state[j + 3]);
+ if (dump_flag == LRC_CONTEXT_DUMP) {
+ struct page *page = i915_gem_object_get_page(ctx_obj, 1);
+ uint32_t *reg_state = kmap_atomic(page);
+ int j;
+
+ seq_printf(m, "CONTEXT: %s %u\n", ring->name,
+ intel_execlists_ctx_id(ctx_obj));
+
+ for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
+ seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
+ reg_state[j], reg_state[j + 1],
+ reg_state[j + 2], reg_state[j + 3]);
+ }
+ kunmap_atomic(reg_state);
+ } else if (dump_flag == FULL_CONTEXT_DUMP) {
+ seq_printf(m, "Hardware Status Page: %s %u\n",
+ ring->name,
+ intel_execlists_ctx_id(ctx_obj));
+ dump_32_obj(m, ctx_obj, 0, 1);
+ seq_printf(m, "Register State Context: %s %u\n", ring->name,
+ intel_execlists_ctx_id(ctx_obj));
+ dump_32_obj(m, ctx_obj, 1, -1);
}
- kunmap_atomic(reg_state);
seq_putc(m, '\n');
}
@@ -4188,7 +4252,8 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_opregion", i915_opregion, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
- {"i915_dump_lrc", i915_dump_lrc, 0},
+ {"i915_context_dump", i915_dump_lrc, 0, (void *)FULL_CONTEXT_DUMP},
+ {"i915_dump_lrc", i915_dump_lrc, 0, (void *)LRC_CONTEXT_DUMP},
{"i915_execlists", i915_execlists, 0},
{"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
{"i915_swizzle_info", i915_swizzle_info, 0},