@@ -195,15 +195,22 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
int fw_engine)
{
/*
- * WaRsDontPollForAckOnClearingFWBits:vlv
- * Hardware clears ack bits lazily (only when all ack
- * bits become 0) so don't poll for individiual ack
- * bits to be clear here like on other platforms.
+ * WaRsDontPollForAckOnClearingFWBits is not required
+ * here as we only do one bit per engine so, the lazy
+ * clearing of bits is not of our concern.
+ *
+ * XXX Even if we access multi-threaded forcewake registers, we
+ * use only one bit in it (another bit for userspace). Multibit access
+ * is broken on multiple gens (IVB, BDW). See WaRSForceSingleThreadFW.
*/
/* Check for Render Engine */
if (FORCEWAKE_RENDER & fw_engine) {
+ if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) &
+ FORCEWAKE_KERNEL) == 0, FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out: waiting for old Render ack to clear.\n");
+
__raw_i915_write32(dev_priv, FORCEWAKE_VLV,
_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
@@ -217,6 +224,11 @@ static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
/* Check for Media Engine */
if (FORCEWAKE_MEDIA & fw_engine) {
+ if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) &
+ FORCEWAKE_KERNEL) == 0, FORCEWAKE_ACK_TIMEOUT_MS))
+ DRM_ERROR("Timed out: waiting for old media ack to clear.\n");
+
+
__raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
_MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));