| Message ID | 1415226371-1880-3-git-send-email-jbarnes@virtuousgeek.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> On 11/06/2014 12:26 AM, Jesse Barnes wrote: > This is useful for checking things later. > > v2: > - fix hsw infoframe enabled check (Ander) > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index d53ac23..8aa80e1 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -292,6 +292,9 @@ struct intel_crtc_config { > * between pch encoders and cpu encoders. */ > bool has_pch_encoder; > > + /* Are we sending infoframes on the attached port */ > + bool has_infoframe; > + > /* CPU Transcoder for the pipe. Currently this can only differ from the > * pipe on Haswell (where we have a special eDP transcoder). */ > enum transcoder cpu_transcoder; > @@ -543,6 +546,7 @@ struct intel_hdmi { > void (*set_infoframes)(struct drm_encoder *encoder, > bool enable, > struct drm_display_mode *adjusted_mode); > + bool (*infoframe_enabled)(struct drm_encoder *encoder); > }; > > struct intel_dp_mst_encoder; > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index 07b5ebd..994237a 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -166,6 +166,15 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, > POSTING_READ(VIDEO_DIP_CTL); > } > > +static bool g4x_infoframe_enabled(struct drm_encoder *encoder) > +{ > + struct drm_device *dev = encoder->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 val = I915_READ(VIDEO_DIP_CTL); > + > + return val & VIDEO_DIP_ENABLE; > +} > + > static void ibx_write_infoframe(struct drm_encoder *encoder, > enum hdmi_infoframe_type type, > const void *frame, ssize_t len) > @@ -204,6 +213,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, > POSTING_READ(reg); > } > > +static bool ibx_infoframe_enabled(struct drm_encoder *encoder) > +{ > + struct drm_device *dev = encoder->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); > + u32 val = I915_READ(reg); > + > + return val & VIDEO_DIP_ENABLE; > +} > + > static void cpt_write_infoframe(struct drm_encoder *encoder, > enum hdmi_infoframe_type type, > const void *frame, ssize_t len) > @@ -245,6 +265,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, > POSTING_READ(reg); > } > > +static bool cpt_infoframe_enabled(struct drm_encoder *encoder) > +{ > + struct drm_device *dev = encoder->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); > + u32 val = I915_READ(reg); > + > + return val & VIDEO_DIP_ENABLE; > +} > + > static void vlv_write_infoframe(struct drm_encoder *encoder, > enum hdmi_infoframe_type type, > const void *frame, ssize_t len) > @@ -283,6 +314,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, > POSTING_READ(reg); > } > > +static bool vlv_infoframe_enabled(struct drm_encoder *encoder) > +{ > + struct drm_device *dev = encoder->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > + int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); > + u32 val = I915_READ(reg); > + > + return val & VIDEO_DIP_ENABLE; > +} > + > static void hsw_write_infoframe(struct drm_encoder *encoder, > enum hdmi_infoframe_type type, > const void *frame, ssize_t len) > @@ -320,6 +362,18 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, > POSTING_READ(ctl_reg); > } > > +static bool hsw_infoframe_enabled(struct drm_encoder *encoder) > +{ > + struct drm_device *dev = encoder->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); > + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); > + u32 val = I915_READ(ctl_reg); > + > + return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | > + VIDEO_DIP_ENABLE_VS_HSW); > +} > + > /* > * The data we write to the DIP data buffer registers is 1 byte bigger than the > * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting > @@ -732,6 +786,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, > if (tmp & HDMI_MODE_SELECT_HDMI) > pipe_config->has_hdmi_sink = true; > > + if (intel_hdmi->infoframe_enabled(&encoder->base)) > + pipe_config->has_infoframe = true; > + > if (tmp & SDVO_AUDIO_ENABLE) > pipe_config->has_audio = true; > > @@ -1616,18 +1673,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, > if (IS_VALLEYVIEW(dev)) { > intel_hdmi->write_infoframe = vlv_write_infoframe; > intel_hdmi->set_infoframes = vlv_set_infoframes; > + intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; > } else if (IS_G4X(dev)) { > intel_hdmi->write_infoframe = g4x_write_infoframe; > intel_hdmi->set_infoframes = g4x_set_infoframes; > + intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; > } else if (HAS_DDI(dev)) { > intel_hdmi->write_infoframe = hsw_write_infoframe; > intel_hdmi->set_infoframes = hsw_set_infoframes; > + intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; > } else if (HAS_PCH_IBX(dev)) { > intel_hdmi->write_infoframe = ibx_write_infoframe; > intel_hdmi->set_infoframes = ibx_set_infoframes; > + intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; > } else { > intel_hdmi->write_infoframe = cpt_write_infoframe; > intel_hdmi->set_infoframes = cpt_set_infoframes; > + intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; > } > > if (HAS_DDI(dev)) >
On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote: > This is useful for checking things later. > > v2: > - fix hsw infoframe enabled check (Ander) > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index d53ac23..8aa80e1 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -292,6 +292,9 @@ struct intel_crtc_config { > * between pch encoders and cpu encoders. */ > bool has_pch_encoder; > > + /* Are we sending infoframes on the attached port */ > + bool has_infoframe; The cross-checking of this new hw state is missing. I've added that while applying. -Daniel
On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote: > On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote: > > This is useful for checking things later. > > > > v2: > > - fix hsw infoframe enabled check (Ander) > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > --- > > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > > drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ > > 2 files changed, 66 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index d53ac23..8aa80e1 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -292,6 +292,9 @@ struct intel_crtc_config { > > * between pch encoders and cpu encoders. */ > > bool has_pch_encoder; > > > > + /* Are we sending infoframes on the attached port */ > > + bool has_infoframe; > > The cross-checking of this new hw state is missing. I've added that while > applying. Where is the compute_config part of this? I can't see it in any patch, but maybe I'm just blind.
On Tue, Nov 11, 2014 at 05:19:46PM +0200, Ville Syrjälä wrote: > On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote: > > On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote: > > > This is useful for checking things later. > > > > > > v2: > > > - fix hsw infoframe enabled check (Ander) > > > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > > --- > > > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > > > drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ > > > 2 files changed, 66 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > > index d53ac23..8aa80e1 100644 > > > --- a/drivers/gpu/drm/i915/intel_drv.h > > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > > @@ -292,6 +292,9 @@ struct intel_crtc_config { > > > * between pch encoders and cpu encoders. */ > > > bool has_pch_encoder; > > > > > > + /* Are we sending infoframes on the attached port */ > > > + bool has_infoframe; > > > > The cross-checking of this new hw state is missing. I've added that while > > applying. > > Where is the compute_config part of this? I can't see it in any patch, > but maybe I'm just blind. Yeah, seems to be missing, thanks for catching this. Jesse/Ander, can you pls supply a fixup quickly - I'd need to drop the series until this one otherwise I think. -Daniel
On Tue, 11 Nov 2014 16:23:03 +0100 Daniel Vetter <daniel@ffwll.ch> wrote: > On Tue, Nov 11, 2014 at 05:19:46PM +0200, Ville Syrjälä wrote: > > On Tue, Nov 11, 2014 at 04:00:12PM +0100, Daniel Vetter wrote: > > > On Wed, Nov 05, 2014 at 02:26:08PM -0800, Jesse Barnes wrote: > > > > This is useful for checking things later. > > > > > > > > v2: > > > > - fix hsw infoframe enabled check (Ander) > > > > > > > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > > > > --- > > > > drivers/gpu/drm/i915/intel_drv.h | 4 +++ > > > > drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ > > > > 2 files changed, 66 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > > > index d53ac23..8aa80e1 100644 > > > > --- a/drivers/gpu/drm/i915/intel_drv.h > > > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > > > @@ -292,6 +292,9 @@ struct intel_crtc_config { > > > > * between pch encoders and cpu encoders. */ > > > > bool has_pch_encoder; > > > > > > > > + /* Are we sending infoframes on the attached port */ > > > > + bool has_infoframe; > > > > > > The cross-checking of this new hw state is missing. I've added that while > > > applying. > > > > Where is the compute_config part of this? I can't see it in any patch, > > but maybe I'm just blind. > > Yeah, seems to be missing, thanks for catching this. Jesse/Ander, can you > pls supply a fixup quickly - I'd need to drop the series until this one > otherwise I think. Ah right missed the other side. Will post a patch today. Thanks,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d53ac23..8aa80e1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -292,6 +292,9 @@ struct intel_crtc_config { * between pch encoders and cpu encoders. */ bool has_pch_encoder; + /* Are we sending infoframes on the attached port */ + bool has_infoframe; + /* CPU Transcoder for the pipe. Currently this can only differ from the * pipe on Haswell (where we have a special eDP transcoder). */ enum transcoder cpu_transcoder; @@ -543,6 +546,7 @@ struct intel_hdmi { void (*set_infoframes)(struct drm_encoder *encoder, bool enable, struct drm_display_mode *adjusted_mode); + bool (*infoframe_enabled)(struct drm_encoder *encoder); }; struct intel_dp_mst_encoder; diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 07b5ebd..994237a 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -166,6 +166,15 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, POSTING_READ(VIDEO_DIP_CTL); } +static bool g4x_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 val = I915_READ(VIDEO_DIP_CTL); + + return val & VIDEO_DIP_ENABLE; +} + static void ibx_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -204,6 +213,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool ibx_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void cpt_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -245,6 +265,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool cpt_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void vlv_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -283,6 +314,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, POSTING_READ(reg); } +static bool vlv_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); + u32 val = I915_READ(reg); + + return val & VIDEO_DIP_ENABLE; +} + static void hsw_write_infoframe(struct drm_encoder *encoder, enum hdmi_infoframe_type type, const void *frame, ssize_t len) @@ -320,6 +362,18 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, POSTING_READ(ctl_reg); } +static bool hsw_infoframe_enabled(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); + u32 val = I915_READ(ctl_reg); + + return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | + VIDEO_DIP_ENABLE_VS_HSW); +} + /* * The data we write to the DIP data buffer registers is 1 byte bigger than the * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting @@ -732,6 +786,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, if (tmp & HDMI_MODE_SELECT_HDMI) pipe_config->has_hdmi_sink = true; + if (intel_hdmi->infoframe_enabled(&encoder->base)) + pipe_config->has_infoframe = true; + if (tmp & SDVO_AUDIO_ENABLE) pipe_config->has_audio = true; @@ -1616,18 +1673,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, if (IS_VALLEYVIEW(dev)) { intel_hdmi->write_infoframe = vlv_write_infoframe; intel_hdmi->set_infoframes = vlv_set_infoframes; + intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; } else if (IS_G4X(dev)) { intel_hdmi->write_infoframe = g4x_write_infoframe; intel_hdmi->set_infoframes = g4x_set_infoframes; + intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; } else if (HAS_DDI(dev)) { intel_hdmi->write_infoframe = hsw_write_infoframe; intel_hdmi->set_infoframes = hsw_set_infoframes; + intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; } else if (HAS_PCH_IBX(dev)) { intel_hdmi->write_infoframe = ibx_write_infoframe; intel_hdmi->set_infoframes = ibx_set_infoframes; + intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; } else { intel_hdmi->write_infoframe = cpt_write_infoframe; intel_hdmi->set_infoframes = cpt_set_infoframes; + intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; } if (HAS_DDI(dev))
This is useful for checking things later. v2: - fix hsw infoframe enabled check (Ander) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> --- drivers/gpu/drm/i915/intel_drv.h | 4 +++ drivers/gpu/drm/i915/intel_hdmi.c | 62 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+)