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[v5] drm/i915/skl: Implement the skl version of MMIO flips

Message ID 1416495496-15602-1-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien Nov. 20, 2014, 2:58 p.m. UTC 
Because the plane registers are different in Skylake we need to adapt
the MMIO code as well.

v2: Don't introduce yet another vfunc when the direction is do
consolidate the plane updates to use the same code path (Daniel)

v3:
  - Use enum pipe instead of int (Ville)
  - Also update PLANE_STRIDE when the tiling has changed (Ville)
  - Put intel_mark_page_flip_active() in the shared code (Damien)

v4:
  - Remove unused variable

v5:
  - Fix whitespace Vs tabs (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++++++++++++++++++++----
 1 file changed, 57 insertions(+), 7 deletions(-)

Comments

Daniel Vetter Nov. 21, 2014, 5:52 p.m. UTC | #1 
On Thu, Nov 20, 2014 at 02:58:16PM +0000, Damien Lespiau wrote:
> Because the plane registers are different in Skylake we need to adapt
> the MMIO code as well.
> 
> v2: Don't introduce yet another vfunc when the direction is do
> consolidate the plane updates to use the same code path (Daniel)
> 
> v3:
>   - Use enum pipe instead of int (Ville)
>   - Also update PLANE_STRIDE when the tiling has changed (Ville)
>   - Put intel_mark_page_flip_active() in the shared code (Damien)
> 
> v4:
>   - Remove unused variable
> 
> v5:
>   - Fix whitespace Vs tabs (Ville)
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c | 64 ++++++++++++++++++++++++++++++++----
>  1 file changed, 57 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c0af4c6..211243b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9436,22 +9436,50 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
>  		return ring != obj->ring;
>  }
>  
> -static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> +static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
> +{
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
> +	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> +	struct drm_i915_gem_object *obj = intel_fb->obj;
> +	const enum pipe pipe = intel_crtc->pipe;
> +	u32 ctl, stride;
> +
> +	ctl = I915_READ(PLANE_CTL(pipe, 0));
> +	ctl &= ~PLANE_CTL_TILED_MASK;
> +	if (obj->tiling_mode == I915_TILING_X)
> +		ctl |= PLANE_CTL_TILED_X;
> +
> +	/*
> +	 * The stride is either expressed as a multiple of 64 bytes chunks for
> +	 * linear buffers or in number of tiles for tiled buffers.
> +	 */
> +	stride = fb->pitches[0] >> 6;
> +	if (obj->tiling_mode == I915_TILING_X)
> +		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
> +
> +	/*
> +	 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
> +	 * PLANE_SURF updates, the update is then guaranteed to be atomic.
> +	 */
> +	I915_WRITE(PLANE_CTL(pipe, 0), ctl);
> +	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
> +
> +	I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
> +	POSTING_READ(PLANE_SURF(pipe, 0));
> +}
> +
> +static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_device *dev = intel_crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_framebuffer *intel_fb =
>  		to_intel_framebuffer(intel_crtc->base.primary->fb);
>  	struct drm_i915_gem_object *obj = intel_fb->obj;
> -	bool atomic_update;
> -	u32 start_vbl_count;
>  	u32 dspcntr;
>  	u32 reg;
>  
> -	intel_mark_page_flip_active(intel_crtc);
> -
> -	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
> -
>  	reg = DSPCNTR(intel_crtc->plane);
>  	dspcntr = I915_READ(reg);
>  
> @@ -9466,6 +9494,28 @@ static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
>  		   intel_crtc->unpin_work->gtt_offset);
>  	POSTING_READ(DSPSURF(intel_crtc->plane));
>  
> +}
> +
> +/*
> + * XXX: This is the temporary way to update the plane registers until we get
> + * around to using the usual plane update functions for MMIO flips
> + */
> +static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
> +{
> +	struct drm_device *dev = intel_crtc->base.dev;
> +	bool atomic_update;
> +	u32 start_vbl_count;
> +
> +	intel_mark_page_flip_active(intel_crtc);
> +
> +	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
> +
> +	if (INTEL_INFO(dev)->gen >= 9)
> +		skl_do_mmio_flip(intel_crtc);
> +	else
> +		/* use_mmio_flip() retricts MMIO flips to ilk+ */
> +		ilk_do_mmio_flip(intel_crtc);
> +
>  	if (atomic_update)
>  		intel_pipe_update_end(intel_crtc, start_vbl_count);
>  }
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Shuang He Nov. 22, 2014, 11:06 a.m. UTC | #2 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  367/367              367/367
ILK                 -7              373/375              366/375
SNB                                  450/450              450/450
IVB                 -1              502/503              501/503
BYT                 -1              289/289              288/289
HSW                 -3              567/567              564/567
BDW                                  417/417              417/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
ILK  igt_kms_flip_absolute-wf_vblank      PASS(1, M37)      DMESG_WARN(2, M26)
ILK  igt_kms_flip_bcs-flip-vs-modeset-interruptible      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_flip_flip-vs-dpms-off-vs-modeset      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_flip_plain-flip      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_flip_plain-flip-fb-recreate-interruptible      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_flip_wf_vblank-ts-check      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
ILK  igt_kms_pipe_crc_basic_bad-nb-words-1      PASS(1, M37)      DMESG_WARN(1, M26)PASS(1, M26)
IVB  igt_gem_bad_reloc_negative-reloc-lut      PASS(1, M21)      NSPT(2, M34)
BYT  igt_gem_exec_bad_domains_conflicting-write-domain      PASS(1, M36)      TIMEOUT(1, M36)PASS(1, M36)
HSW  igt_gem_bad_reloc_negative-reloc-lut      PASS(1, M20)      NSPT(2, M20)
HSW  igt_kms_rotation_crc_primary-rotation      PASS(1, M20)      DMESG_WARN(1, M20)PASS(1, M20)
HSW  igt_pm_rc6_residency_rc6-accuracy      PASS(1, M20)      FAIL(1, M20)PASS(1, M20)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c0af4c6..211243b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9436,22 +9436,50 @@  static bool use_mmio_flip(struct intel_engine_cs *ring,
 		return ring != obj->ring;
 }
 
-static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
+static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
+{
+	struct drm_device *dev = intel_crtc->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
+	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+	struct drm_i915_gem_object *obj = intel_fb->obj;
+	const enum pipe pipe = intel_crtc->pipe;
+	u32 ctl, stride;
+
+	ctl = I915_READ(PLANE_CTL(pipe, 0));
+	ctl &= ~PLANE_CTL_TILED_MASK;
+	if (obj->tiling_mode == I915_TILING_X)
+		ctl |= PLANE_CTL_TILED_X;
+
+	/*
+	 * The stride is either expressed as a multiple of 64 bytes chunks for
+	 * linear buffers or in number of tiles for tiled buffers.
+	 */
+	stride = fb->pitches[0] >> 6;
+	if (obj->tiling_mode == I915_TILING_X)
+		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
+
+	/*
+	 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
+	 * PLANE_SURF updates, the update is then guaranteed to be atomic.
+	 */
+	I915_WRITE(PLANE_CTL(pipe, 0), ctl);
+	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
+
+	I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
+	POSTING_READ(PLANE_SURF(pipe, 0));
+}
+
+static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_framebuffer *intel_fb =
 		to_intel_framebuffer(intel_crtc->base.primary->fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
-	bool atomic_update;
-	u32 start_vbl_count;
 	u32 dspcntr;
 	u32 reg;
 
-	intel_mark_page_flip_active(intel_crtc);
-
-	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
-
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
@@ -9466,6 +9494,28 @@  static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
 		   intel_crtc->unpin_work->gtt_offset);
 	POSTING_READ(DSPSURF(intel_crtc->plane));
 
+}
+
+/*
+ * XXX: This is the temporary way to update the plane registers until we get
+ * around to using the usual plane update functions for MMIO flips
+ */
+static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
+{
+	struct drm_device *dev = intel_crtc->base.dev;
+	bool atomic_update;
+	u32 start_vbl_count;
+
+	intel_mark_page_flip_active(intel_crtc);
+
+	atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
+
+	if (INTEL_INFO(dev)->gen >= 9)
+		skl_do_mmio_flip(intel_crtc);
+	else
+		/* use_mmio_flip() retricts MMIO flips to ilk+ */
+		ilk_do_mmio_flip(intel_crtc);
+
 	if (atomic_update)
 		intel_pipe_update_end(intel_crtc, start_vbl_count);
 }