Message ID | 1416586496-14341-1-git-send-email-damien.lespiau@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Fri, Nov 21, 2014 at 04:14:56PM +0000, Damien Lespiau wrote: > v2: Put the DPLL0 state readout in skylake_get_ddi_pll(), closer to > where the PLL assignement read out is done rather than the frequency > readout function. (Daniel) > > v3: Remove stray new line (Damien) > Add Paulo's r-b tag for v1 > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> I still think it might be safer to put DPLL0 into the shared infrastructure too just because. But this looks good as-is. Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 853697f..1623178 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7994,12 +7994,21 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_config *pipe_config) { - u32 temp; + u32 temp, dpll_ctl1; temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); switch (pipe_config->ddi_pll_sel) { + case SKL_DPLL0: + /* + * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part + * of the shared DPLL framework and thus needs to be read out + * separately + */ + dpll_ctl1 = I915_READ(DPLL_CTRL1); + pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; + break; case SKL_DPLL1: pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; break;