From patchwork Wed Dec 3 18:10:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Taylor, Clinton A" X-Patchwork-Id: 5432891 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BB59ABEEA8 for ; Wed, 3 Dec 2014 19:49:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EC24620357 for ; Wed, 3 Dec 2014 19:49:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 16FCA20374 for ; Wed, 3 Dec 2014 19:49:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 882F76E142; Wed, 3 Dec 2014 11:49:17 -0800 (PST) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id F3C1B6E199 for ; Wed, 3 Dec 2014 11:49:15 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 03 Dec 2014 10:12:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,509,1413270000"; d="scan'208";a="632119481" Received: from cataylo2-ubuntu64-12.jf.intel.com ([134.134.145.123]) by fmsmga001.fm.intel.com with ESMTP; 03 Dec 2014 10:12:00 -0800 From: clinton.a.taylor@intel.com To: Intel-gfx@lists.freedesktop.org Date: Wed, 3 Dec 2014 10:10:30 -0800 Message-Id: <1417630230-3171-1-git-send-email-clinton.a.taylor@intel.com> X-Mailer: git-send-email 1.7.9.5 Subject: [Intel-gfx] [PATCH] drm/i915/chv: Enable HDMI Clock recovery for Pipe C X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Clint Taylor Added PIPE C register support for CHV audio programming. Signed-off-by: Clint Taylor --- drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index dc03fac..3d5813a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6189,14 +6189,18 @@ enum punit_power_well { #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050) #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150) -#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \ +#define _CHV_HDMIW_HDMIEDID_C (VLV_DISPLAY_BASE + 0x62250) +#define VLV_HDMIW_HDMIEDID(pipe) _PIPE3(pipe, \ _VLV_HDMIW_HDMIEDID_A, \ - _VLV_HDMIW_HDMIEDID_B) + _VLV_HDMIW_HDMIEDID_B, \ + _CHV_HDMIW_HDMIEDID_C) #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4) #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4) -#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \ +#define _CHV_AUD_CNTL_ST_C (VLV_DISPLAY_BASE + 0x622B4) +#define VLV_AUD_CNTL_ST(pipe) _PIPE3(pipe, \ _VLV_AUD_CNTL_ST_A, \ - _VLV_AUD_CNTL_ST_B) + _VLV_AUD_CNTL_ST_B, \ + _CHV_AUD_CNTL_ST_C) #define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0) /* These are the 4 32-bit write offset registers for each stream @@ -6217,9 +6221,11 @@ enum punit_power_well { _CPT_AUD_CONFIG_B) #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000) #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100) -#define VLV_AUD_CFG(pipe) _PIPE(pipe, \ +#define _CHV_AUD_CONFIG_C (VLV_DISPLAY_BASE + 0x62200) +#define VLV_AUD_CFG(pipe) _PIPE3(pipe, \ _VLV_AUD_CONFIG_A, \ - _VLV_AUD_CONFIG_B) + _VLV_AUD_CONFIG_B, \ + _CHV_AUD_CONFIG_C) #define AUD_CONFIG_N_VALUE_INDEX (1 << 29) #define AUD_CONFIG_N_PROG_ENABLE (1 << 28)