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[3/4] drm/i915: Enable MIPI PHY transparent latch for DSI Port C

Message ID 1417949035-32199-4-git-send-email-gaurav.k.singh@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Gaurav K Singh Dec. 7, 2014, 10:43 a.m. UTC 
Common bit to be used for both DSI Port A & DSI Port C.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Jani Nikula Dec. 9, 2014, 8:36 a.m. UTC | #1 
On Sun, 07 Dec 2014, Gaurav K Singh <gaurav.k.singh@intel.com> wrote:
> Common bit to be used for both DSI Port A & DSI Port C.
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>

At some point I'd like to have the bits specific to port A only
extracted outside of the for loop, but this is fine for now.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi.c |    7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 8f8b952..215d004 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -177,7 +177,12 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  		usleep_range(2500, 3000);
>  
>  		val = I915_READ(MIPI_PORT_CTRL(port));
> -		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> +
> +		/* Enable MIPI PHY transparent latch
> +		 * Common bit for both MIPI Port A & MIPI Port C
> +		 * No similar bit in MIPI Port C reg
> +		 */
> +		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
>  		usleep_range(1000, 1500);
>  
>  		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> -- 
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8f8b952..215d004 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -177,7 +177,12 @@  static void intel_dsi_device_ready(struct intel_encoder *encoder)
 		usleep_range(2500, 3000);
 
 		val = I915_READ(MIPI_PORT_CTRL(port));
-		I915_WRITE(MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+
+		/* Enable MIPI PHY transparent latch
+		 * Common bit for both MIPI Port A & MIPI Port C
+		 * No similar bit in MIPI Port C reg
+		 */
+		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
 		usleep_range(1000, 1500);
 
 		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);