Message ID | 1418063262-32256-7-git-send-email-mika.kuoppala@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Monday 08 December 2014 11:57 PM, Mika Kuoppala wrote: > We have multiple forcewake domains now on recent gens. Change the > function naming to reflect this. > > v2: More verbose names (Chris) > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++---- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 15 +++++---------- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > drivers/gpu/drm/i915/intel_lrc.c | 4 ++-- > drivers/gpu/drm/i915/intel_pm.c | 28 ++++++++++++++-------------- > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- > drivers/gpu/drm/i915/intel_uncore.c | 18 +++++++++--------- > 8 files changed, 39 insertions(+), 44 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 93390c9..ecc4b42 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1052,7 +1052,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > if (ret) > goto out; > > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > reqf = I915_READ(GEN6_RPNSWREQ); > reqf &= ~GEN6_TURBO_DISABLE; > @@ -1079,7 +1079,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; > cagf *= GT_FREQUENCY_MULTIPLIER; > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > mutex_unlock(&dev->struct_mutex); > > if (IS_GEN6(dev) || IS_GEN7(dev)) { > @@ -4233,7 +4233,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) > return 0; > > intel_runtime_pm_get(dev_priv); > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > return 0; > } > @@ -4246,7 +4246,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) > if (INTEL_INFO(dev)->gen < 6) > return 0; > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > intel_runtime_pm_put(dev_priv); > > return 0; > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 706b122..011caa2 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1362,7 +1362,7 @@ static int intel_runtime_suspend(struct device *device) > if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) > return -ENODEV; > > - assert_force_wake_inactive(dev_priv); > + assert_forcewakes_inactive(dev_priv); > > DRM_DEBUG_KMS("Suspending device\n"); > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 4263084..a2a8536 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2450,6 +2450,11 @@ extern void intel_uncore_check_errors(struct drm_device *dev); > extern void intel_uncore_fini(struct drm_device *dev); > extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); > const char *intel_uncore_forcewake_domain_to_str(const int domain_id); > +void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, > + unsigned fw_domains); > +void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, > + unsigned fw_domains); > +void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); > > void > i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, > @@ -3026,16 +3031,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, > struct drm_device *dev, > struct intel_display_error_state *error); > > -/* On SNB platform, before reading ring registers forcewake bit > - * must be set to prevent GT core from power down and stale values being > - * returned. > - */ > -void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, > - unsigned fw_domains); > -void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, > - unsigned fw_domains); > -void assert_force_wake_inactive(struct drm_i915_private *dev_priv); > - > int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); > int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 86c2885..d2d60f0 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7863,7 +7863,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) > * Make sure we're not on PC8 state before disabling PC8, otherwise > * we'll hang the machine. To prevent PC8 state, just enable force_wake. > */ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > if (val & LCPLL_POWER_DOWN_ALLOW) { > val &= ~LCPLL_POWER_DOWN_ALLOW; > @@ -7893,7 +7893,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) > DRM_ERROR("Switching back to LCPLL failed\n"); > } > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > /* > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index fcb5140..be9d00b 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -297,7 +297,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, > desc[3] = (u32)(temp >> 32); > desc[2] = (u32)temp; > > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > I915_WRITE(RING_ELSP(ring), desc[1]); > I915_WRITE(RING_ELSP(ring), desc[0]); > I915_WRITE(RING_ELSP(ring), desc[3]); > @@ -307,7 +307,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, > > /* ELSP is a wo register, so use another nearby reg for posting instead */ > POSTING_READ(RING_EXECLIST_STATUS(ring)); > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 78911e2..64e06a3 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -228,7 +228,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) > > /* Blitter is part of Media powerwell on VLV. No impact of > * his param in other platforms for now */ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); > > blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); > blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << > @@ -241,7 +241,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) > I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); > POSTING_READ(GEN6_BLITTER_ECOSKPD); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); > } > > static void ironlake_enable_fbc(struct drm_crtc *crtc) > @@ -4541,11 +4541,11 @@ static void valleyview_disable_rps(struct drm_device *dev) > > /* we're doing forcewake before Disabling RC6, > * This what the BIOS expects when going into suspend */ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > I915_WRITE(GEN6_RC_CONTROL, 0); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > static void intel_print_rc6_info(struct drm_device *dev, u32 mode) > @@ -4663,7 +4663,7 @@ static void gen9_enable_rps(struct drm_device *dev) > > /* 1b: Get forcewake during program sequence. Although the driver > * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* 2a: Disable RC states. */ > I915_WRITE(GEN6_RC_CONTROL, 0); > @@ -4686,7 +4686,7 @@ static void gen9_enable_rps(struct drm_device *dev) > GEN6_RC_CTL_EI_MODE(1) | > rc6_mask); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > } > > @@ -4702,7 +4702,7 @@ static void gen8_enable_rps(struct drm_device *dev) > > /* 1c & 1d: Get forcewake during program sequence. Although the driver > * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* 2a: Disable RC states. */ > I915_WRITE(GEN6_RC_CONTROL, 0); > @@ -4769,7 +4769,7 @@ static void gen8_enable_rps(struct drm_device *dev) > dev_priv->rps.power = HIGH_POWER; /* force a reset */ > gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > static void gen6_enable_rps(struct drm_device *dev) > @@ -4797,7 +4797,7 @@ static void gen6_enable_rps(struct drm_device *dev) > I915_WRITE(GTFIFODBG, gtfifodbg); > } > > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* Initialize rps frequencies */ > gen6_init_rps_frequencies(dev); > @@ -4877,7 +4877,7 @@ static void gen6_enable_rps(struct drm_device *dev) > DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); > } > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > static void __gen6_update_ring_freq(struct drm_device *dev) > @@ -5296,7 +5296,7 @@ static void cherryview_enable_rps(struct drm_device *dev) > > /* 1a & 1b: Get forcewake during program sequence. Although the driver > * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* 2a: Program RC6 thresholds.*/ > I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); > @@ -5364,7 +5364,7 @@ static void cherryview_enable_rps(struct drm_device *dev) > > valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > static void valleyview_enable_rps(struct drm_device *dev) > @@ -5385,7 +5385,7 @@ static void valleyview_enable_rps(struct drm_device *dev) > } > > /* If VLV, Forcewake all wells, else re-direct to regular path */ > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); > I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); > @@ -5445,7 +5445,7 @@ static void valleyview_enable_rps(struct drm_device *dev) > > valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); > > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > } > > void ironlake_teardown_rc6(struct drm_device *dev) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 3887f1a..210728f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -536,7 +536,7 @@ static int init_ring_common(struct intel_engine_cs *ring) > struct drm_i915_gem_object *obj = ringbuf->obj; > int ret = 0; > > - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > if (!stop_ring(ring)) { > /* G45 ring initialization often fails to reset head to zero */ > @@ -608,7 +608,7 @@ static int init_ring_common(struct intel_engine_cs *ring) > memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); > > out: > - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > > return ret; > } > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 8021bec..509b9c9 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -232,7 +232,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) > return ret; > } > > -static void gen6_force_wake_timer(unsigned long arg) > +static void intel_uncore_fw_release_timer(unsigned long arg) > { > struct intel_uncore_forcewake_domain *domain = (void *)arg; > unsigned long irqflags; > @@ -326,10 +326,10 @@ void intel_uncore_sanitize(struct drm_device *dev) > * Generally this is called implicitly by the register read function. However, > * if some sequence requires the GT to not power down then this function should > * be called at the beginning of the sequence followed by a call to > - * gen6_gt_force_wake_put() at the end of the sequence. > + * intel_uncore_forcewake_put() at the end of the sequence. > */ > -void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, > - unsigned fw_domains) > +void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, > + unsigned fw_domains) > { > unsigned long irqflags; > struct intel_uncore_forcewake_domain *domain; > @@ -355,10 +355,10 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, > } > > /* > - * see gen6_gt_force_wake_get() > + * see intel_uncore_forcewake_get() > */ > -void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, > - unsigned fw_domains) > +void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, > + unsigned fw_domains) > { > unsigned long irqflags; > struct intel_uncore_forcewake_domain *domain; > @@ -383,7 +383,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > } > > -void assert_force_wake_inactive(struct drm_i915_private *dev_priv) > +void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) > { > struct intel_uncore_forcewake_domain *domain; > int id; > @@ -924,7 +924,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv, > d->i915 = dev_priv; > d->id = domain_id; > > - setup_timer(&d->timer, gen6_force_wake_timer, (unsigned long)d); > + setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d); > > dev_priv->uncore.fw_domains |= (1 << domain_id); > } Looks fine Reviewed-by: Deepak S<deepak.s@linux.intel.com>
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 93390c9..ecc4b42 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1052,7 +1052,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) if (ret) goto out; - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); reqf = I915_READ(GEN6_RPNSWREQ); reqf &= ~GEN6_TURBO_DISABLE; @@ -1079,7 +1079,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; cagf *= GT_FREQUENCY_MULTIPLIER; - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); mutex_unlock(&dev->struct_mutex); if (IS_GEN6(dev) || IS_GEN7(dev)) { @@ -4233,7 +4233,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) return 0; intel_runtime_pm_get(dev_priv); - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); return 0; } @@ -4246,7 +4246,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) if (INTEL_INFO(dev)->gen < 6) return 0; - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); intel_runtime_pm_put(dev_priv); return 0; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 706b122..011caa2 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1362,7 +1362,7 @@ static int intel_runtime_suspend(struct device *device) if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) return -ENODEV; - assert_force_wake_inactive(dev_priv); + assert_forcewakes_inactive(dev_priv); DRM_DEBUG_KMS("Suspending device\n"); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4263084..a2a8536 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2450,6 +2450,11 @@ extern void intel_uncore_check_errors(struct drm_device *dev); extern void intel_uncore_fini(struct drm_device *dev); extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); const char *intel_uncore_forcewake_domain_to_str(const int domain_id); +void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, + unsigned fw_domains); +void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, + unsigned fw_domains); +void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); void i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, @@ -3026,16 +3031,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, struct drm_device *dev, struct intel_display_error_state *error); -/* On SNB platform, before reading ring registers forcewake bit - * must be set to prevent GT core from power down and stale values being - * returned. - */ -void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, - unsigned fw_domains); -void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, - unsigned fw_domains); -void assert_force_wake_inactive(struct drm_i915_private *dev_priv); - int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 86c2885..d2d60f0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7863,7 +7863,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) * Make sure we're not on PC8 state before disabling PC8, otherwise * we'll hang the machine. To prevent PC8 state, just enable force_wake. */ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); if (val & LCPLL_POWER_DOWN_ALLOW) { val &= ~LCPLL_POWER_DOWN_ALLOW; @@ -7893,7 +7893,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) DRM_ERROR("Switching back to LCPLL failed\n"); } - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } /* diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fcb5140..be9d00b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -297,7 +297,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, desc[3] = (u32)(temp >> 32); desc[2] = (u32)temp; - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); I915_WRITE(RING_ELSP(ring), desc[1]); I915_WRITE(RING_ELSP(ring), desc[0]); I915_WRITE(RING_ELSP(ring), desc[3]); @@ -307,7 +307,7 @@ static void execlists_elsp_write(struct intel_engine_cs *ring, /* ELSP is a wo register, so use another nearby reg for posting instead */ POSTING_READ(RING_EXECLIST_STATUS(ring)); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 78911e2..64e06a3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -228,7 +228,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) /* Blitter is part of Media powerwell on VLV. No impact of * his param in other platforms for now */ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << @@ -241,7 +241,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); POSTING_READ(GEN6_BLITTER_ECOSKPD); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); } static void ironlake_enable_fbc(struct drm_crtc *crtc) @@ -4541,11 +4541,11 @@ static void valleyview_disable_rps(struct drm_device *dev) /* we're doing forcewake before Disabling RC6, * This what the BIOS expects when going into suspend */ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); I915_WRITE(GEN6_RC_CONTROL, 0); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } static void intel_print_rc6_info(struct drm_device *dev, u32 mode) @@ -4663,7 +4663,7 @@ static void gen9_enable_rps(struct drm_device *dev) /* 1b: Get forcewake during program sequence. Although the driver * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* 2a: Disable RC states. */ I915_WRITE(GEN6_RC_CONTROL, 0); @@ -4686,7 +4686,7 @@ static void gen9_enable_rps(struct drm_device *dev) GEN6_RC_CTL_EI_MODE(1) | rc6_mask); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } @@ -4702,7 +4702,7 @@ static void gen8_enable_rps(struct drm_device *dev) /* 1c & 1d: Get forcewake during program sequence. Although the driver * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* 2a: Disable RC states. */ I915_WRITE(GEN6_RC_CONTROL, 0); @@ -4769,7 +4769,7 @@ static void gen8_enable_rps(struct drm_device *dev) dev_priv->rps.power = HIGH_POWER; /* force a reset */ gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } static void gen6_enable_rps(struct drm_device *dev) @@ -4797,7 +4797,7 @@ static void gen6_enable_rps(struct drm_device *dev) I915_WRITE(GTFIFODBG, gtfifodbg); } - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* Initialize rps frequencies */ gen6_init_rps_frequencies(dev); @@ -4877,7 +4877,7 @@ static void gen6_enable_rps(struct drm_device *dev) DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); } - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } static void __gen6_update_ring_freq(struct drm_device *dev) @@ -5296,7 +5296,7 @@ static void cherryview_enable_rps(struct drm_device *dev) /* 1a & 1b: Get forcewake during program sequence. Although the driver * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* 2a: Program RC6 thresholds.*/ I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); @@ -5364,7 +5364,7 @@ static void cherryview_enable_rps(struct drm_device *dev) valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } static void valleyview_enable_rps(struct drm_device *dev) @@ -5385,7 +5385,7 @@ static void valleyview_enable_rps(struct drm_device *dev) } /* If VLV, Forcewake all wells, else re-direct to regular path */ - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); @@ -5445,7 +5445,7 @@ static void valleyview_enable_rps(struct drm_device *dev) valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); } void ironlake_teardown_rc6(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3887f1a..210728f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -536,7 +536,7 @@ static int init_ring_common(struct intel_engine_cs *ring) struct drm_i915_gem_object *obj = ringbuf->obj; int ret = 0; - gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); if (!stop_ring(ring)) { /* G45 ring initialization often fails to reset head to zero */ @@ -608,7 +608,7 @@ static int init_ring_common(struct intel_engine_cs *ring) memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); out: - gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return ret; } diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 8021bec..509b9c9 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -232,7 +232,7 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) return ret; } -static void gen6_force_wake_timer(unsigned long arg) +static void intel_uncore_fw_release_timer(unsigned long arg) { struct intel_uncore_forcewake_domain *domain = (void *)arg; unsigned long irqflags; @@ -326,10 +326,10 @@ void intel_uncore_sanitize(struct drm_device *dev) * Generally this is called implicitly by the register read function. However, * if some sequence requires the GT to not power down then this function should * be called at the beginning of the sequence followed by a call to - * gen6_gt_force_wake_put() at the end of the sequence. + * intel_uncore_forcewake_put() at the end of the sequence. */ -void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, - unsigned fw_domains) +void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, + unsigned fw_domains) { unsigned long irqflags; struct intel_uncore_forcewake_domain *domain; @@ -355,10 +355,10 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, } /* - * see gen6_gt_force_wake_get() + * see intel_uncore_forcewake_get() */ -void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, - unsigned fw_domains) +void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, + unsigned fw_domains) { unsigned long irqflags; struct intel_uncore_forcewake_domain *domain; @@ -383,7 +383,7 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } -void assert_force_wake_inactive(struct drm_i915_private *dev_priv) +void assert_forcewakes_inactive(struct drm_i915_private *dev_priv) { struct intel_uncore_forcewake_domain *domain; int id; @@ -924,7 +924,7 @@ static void fw_domain_init(struct drm_i915_private *dev_priv, d->i915 = dev_priv; d->id = domain_id; - setup_timer(&d->timer, gen6_force_wake_timer, (unsigned long)d); + setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d); dev_priv->uncore.fw_domains |= (1 << domain_id); }
We have multiple forcewake domains now on recent gens. Change the function naming to reflect this. v2: More verbose names (Chris) Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 8 ++++---- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 15 +++++---------- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_lrc.c | 4 ++-- drivers/gpu/drm/i915/intel_pm.c | 28 ++++++++++++++-------------- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 18 +++++++++--------- 8 files changed, 39 insertions(+), 44 deletions(-)