From patchwork Fri Dec 12 16:53:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 5484151 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3FCFD9F30B for ; Fri, 12 Dec 2014 16:50:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B2F8B201D3 for ; Fri, 12 Dec 2014 16:50:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 23D9920122 for ; Fri, 12 Dec 2014 16:50:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BD21A6E17D; Fri, 12 Dec 2014 08:50:50 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id DBDA16E17D for ; Fri, 12 Dec 2014 08:50:48 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 12 Dec 2014 08:49:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,565,1413270000"; d="scan'208";a="636744589" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.102]) by fmsmga001.fm.intel.com with ESMTP; 12 Dec 2014 08:49:03 -0800 Received: by rosetta (Postfix, from userid 1000) id 7052080052; Fri, 12 Dec 2014 18:53:15 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Dec 2014 18:53:14 +0200 Message-Id: <1418403194-4093-1-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] tests: Add gem_blt_copy_align test X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Copy a block into destination object with varying dst/src offsets. Put guard area before and after the blit target to see that it didn't touch memory out of blit boundaries. References: https://bugs.freedesktop.org/show_bug.cgi?id=79053 Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- gem_blt_copy_align.c | 230 +++++++++++++++++++++++++++++++++++++++++++ tests/Makefile.sources | 1 + tests/gem_blt_copy_align.c | 237 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 468 insertions(+) create mode 100644 gem_blt_copy_align.c create mode 100644 tests/gem_blt_copy_align.c diff --git a/gem_blt_copy_align.c b/gem_blt_copy_align.c new file mode 100644 index 0000000..84693da --- /dev/null +++ b/gem_blt_copy_align.c @@ -0,0 +1,230 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Chris Wilson + * Mika Kuoppala + * + */ + +#include +#include +#include +#include "i915_drm.h" +#include "intel_chipset.h" +#include "intel_reg.h" +#include "ioctl_wrappers.h" +#include "drm.h" +#include "drmtest.h" + +static int gen = 0; + +#define WIDTH 32 +#define HEIGHT 32 + +static uint32_t linear[WIDTH*HEIGHT]; + +static void +copy_align(int fd, + uint32_t dst, uint32_t dst_offset, + uint32_t src, uint32_t src_offset, + uint32_t w, uint32_t h) +{ + uint32_t batch[12]; + struct drm_i915_gem_relocation_entry reloc[2]; + struct drm_i915_gem_exec_object2 obj[3]; + struct drm_i915_gem_execbuffer2 exec; + uint32_t handle; + int i=0; + + batch[i++] = XY_SRC_COPY_BLT_CMD | + XY_SRC_COPY_BLT_WRITE_ALPHA | + XY_SRC_COPY_BLT_WRITE_RGB; + if (gen >= 8) + batch[i - 1] |= 8; + else + batch[i - 1] |= 6; + + batch[i++] = (3 << 24) | /* 32 bits */ + (0xcc << 16) | /* copy ROP */ + w * 4; + + /* The >= gen8 blitter needs to have dst/src base + * addresses aligned to 4k. So we need to handle the + * offsets with with dst/src coordinates */ + batch[i++] = dst_offset; /* dst, x1,y2 */ + batch[i++] = ((h) << 16) | (w + dst_offset); /* dst x2,y2 */ + batch[i++] = 0; + if (gen >= 8) + batch[i++] = 0; + batch[i++] = src_offset; /* src x1,y1 */ + batch[i++] = w * 4; + +#if 0 + /* Bspec says this should be aligned to quad with gen8 but it doesn't + seem to matter */ + if (gen >= 8 && (w * 4) % 8) + igt_warn("src pitch NOT aligned to quad\n"); +#endif + + batch[i++] = 0; + if (gen >= 8) + batch[i++] = 0; + + batch[i++] = MI_BATCH_BUFFER_END; + batch[i++] = MI_NOOP; + + handle = gem_create(fd, 4096); + gem_write(fd, handle, 0, batch, sizeof(batch)); + + reloc[0].target_handle = dst; + reloc[0].delta = 0; + reloc[0].offset = 4 * sizeof(batch[0]); + reloc[0].presumed_offset = 0; + reloc[0].read_domains = I915_GEM_DOMAIN_RENDER; + reloc[0].write_domain = I915_GEM_DOMAIN_RENDER; + + reloc[1].target_handle = src; + reloc[1].delta = 0; + reloc[1].offset = 7 * sizeof(batch[0]); + if (gen >= 8) + reloc[1].offset += sizeof(batch[0]); + reloc[1].presumed_offset = 0; + reloc[1].read_domains = I915_GEM_DOMAIN_RENDER; + reloc[1].write_domain = 0; + + memset(obj, 0, sizeof(obj)); + exec.buffer_count = 0; + obj[exec.buffer_count++].handle = dst; + if (src != dst) + obj[exec.buffer_count++].handle = src; + obj[exec.buffer_count].handle = handle; + obj[exec.buffer_count].relocation_count = 2; + obj[exec.buffer_count].relocs_ptr = (uintptr_t)reloc; + exec.buffer_count++; + exec.buffers_ptr = (uintptr_t)obj; + + exec.batch_start_offset = 0; + exec.batch_len = i * 4; + exec.DR1 = exec.DR4 = 0; + exec.num_cliprects = 0; + exec.cliprects_ptr = 0; + exec.flags = HAS_BLT_RING(intel_get_drm_devid(fd)) ? I915_EXEC_BLT : 0; + i915_execbuffer2_set_context_id(exec, 0); + exec.rsvd2 = 0; + + gem_execbuf(fd, &exec); + + gem_sync(fd, handle); + gem_close(fd, handle); +} + +static bool area_ok(uint32_t *p, const int size, const uint32_t sval) +{ + int i; + + for (i = 0; i < size; i++) + if (p[i] != i + sval) + return false; + + return true; +} + +static void +_test_destination_align(int fd, + const uint32_t dst_align, const uint32_t src_align, + const uint32_t w, const uint32_t h) +{ + const uint32_t size = sizeof(linear) / 4; + const uint32_t guard_val = 0xdeadf00d; + uint32_t *p; + uint32_t h_dst; + uint32_t h_src; + int i; + const int dwords = w * h; + + igt_assert(dwords < size); + p = linear; + + h_src = gem_create(fd, size * 4); + igt_assert(h_src != 0); + + for (i = 0; i < size; i++) + p[i] = i; + + gem_write(fd, h_src, 0, p, size * 4); + gem_read(fd, h_src, 0, p, size * 4); + + igt_assert(area_ok(p, size, 0)); + + h_dst = gem_create(fd, size * 4); + igt_assert(h_dst != 0); + + for (i = 0; i < size; i++) + p[i] = guard_val + i; + + gem_write(fd, h_dst, 0, p, size * 4); + gem_read(fd, h_dst, 0, p, size * 4); + + igt_assert(area_ok(p, size, guard_val)); + + copy_align(fd, h_dst, dst_align, h_src, src_align, w, h); + gem_read(fd, h_dst, 0, p, size * 4); + + igt_assert(area_ok(p, dst_align, guard_val)); + igt_assert(area_ok(p + dst_align, dwords, src_align)); + igt_assert(area_ok(p + dwords + dst_align, + size - dwords - dst_align, + guard_val + dwords + dst_align)); + + gem_close(fd, h_src); + gem_close(fd, h_dst); +} + +static void test_destination_align(int fd, + int dst_align, int src_align, + int max_w, int max_h) +{ + int i, j, w, h; + + for (i = 0; i <= src_align; i++) + for (j = 0; j <= dst_align; j++) + for (h = 1; h <= max_h; h ++) + for (w = 1; w <= max_w; w++) + _test_destination_align(fd, j, i, w, h); +} + +igt_simple_main +{ + int fd = -1; + + igt_skip_on_simulation(); + + igt_fixture { + fd = drm_open_any(); + igt_assert(fd >= 0); + + gen = intel_gen(intel_get_drm_devid(fd)); + } + + test_destination_align(fd, 16, 16, 16, 16); +} diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 967dc8f..acc32be 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -119,6 +119,7 @@ TESTS_progs = \ gem_render_copy \ gem_render_linear_blits \ gem_render_tiled_blits \ + gem_blt_copy_align \ gem_ring_sync_copy \ gem_ring_sync_loop \ gem_multi_bsd_sync_loop \ diff --git a/tests/gem_blt_copy_align.c b/tests/gem_blt_copy_align.c new file mode 100644 index 0000000..de3ea21 --- /dev/null +++ b/tests/gem_blt_copy_align.c @@ -0,0 +1,237 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Chris Wilson + * Mika Kuoppala + * + */ + +#include +#include +#include +#include "i915_drm.h" +#include "intel_chipset.h" +#include "intel_reg.h" +#include "ioctl_wrappers.h" +#include "drm.h" +#include "drmtest.h" + +static int gen = 0; + +#define WIDTH 32 +#define HEIGHT 32 + +static uint32_t linear[WIDTH * HEIGHT]; + +static void +copy_align(int fd, + uint32_t dst, uint32_t dst_offset, + uint32_t src, uint32_t src_offset, + uint32_t w, uint32_t h) +{ + uint32_t batch[12]; + struct drm_i915_gem_relocation_entry reloc[2]; + struct drm_i915_gem_exec_object2 obj[3]; + struct drm_i915_gem_execbuffer2 exec; + uint32_t handle; + int i=0; + + batch[i++] = XY_SRC_COPY_BLT_CMD | + XY_SRC_COPY_BLT_WRITE_ALPHA | + XY_SRC_COPY_BLT_WRITE_RGB; + if (gen >= 8) + batch[i - 1] |= 8; + else + batch[i - 1] |= 6; + + batch[i++] = (3 << 24) | /* 32 bits */ + (0xcc << 16) | /* copy ROP */ + w * 4; + + /* The >= gen8 blitter needs to have dst/src base + * addresses aligned to 4k. So we need to handle the + * offsets with with dst/src coordinates */ + + batch[i++] = dst_offset; /* dst, x1,y2 */ + batch[i++] = ((h) << 16) | (w + dst_offset); /* dst x2,y2 */ + batch[i++] = 0; + if (gen >= 8) + batch[i++] = 0; + batch[i++] = src_offset; /* src x1,y1 */ + batch[i++] = w * 4; + +#if 0 + /* Bspec says this should be aligned to quad with gen8 but it doesn't + seem to matter on */ + if (gen >= 8 && (w * 4) % 8) + igt_warn("src pitch NOT aligned to quad\n"); +#endif + + batch[i++] = 0; + if (gen >= 8) + batch[i++] = 0; + + batch[i++] = MI_BATCH_BUFFER_END; + batch[i++] = MI_NOOP; + + handle = gem_create(fd, 4096); + gem_write(fd, handle, 0, batch, sizeof(batch)); + + reloc[0].target_handle = dst; + reloc[0].delta = 0; + reloc[0].offset = 4 * sizeof(batch[0]); + reloc[0].presumed_offset = 0; + reloc[0].read_domains = I915_GEM_DOMAIN_RENDER; + reloc[0].write_domain = I915_GEM_DOMAIN_RENDER; + + reloc[1].target_handle = src; + reloc[1].delta = 0; + reloc[1].offset = 7 * sizeof(batch[0]); + if (gen >= 8) + reloc[1].offset += sizeof(batch[0]); + reloc[1].presumed_offset = 0; + reloc[1].read_domains = I915_GEM_DOMAIN_RENDER; + reloc[1].write_domain = 0; + + memset(obj, 0, sizeof(obj)); + exec.buffer_count = 0; + obj[exec.buffer_count++].handle = dst; + if (src != dst) + obj[exec.buffer_count++].handle = src; + obj[exec.buffer_count].handle = handle; + obj[exec.buffer_count].relocation_count = 2; + obj[exec.buffer_count].relocs_ptr = (uintptr_t)reloc; + exec.buffer_count++; + exec.buffers_ptr = (uintptr_t)obj; + + exec.batch_start_offset = 0; + exec.batch_len = i * 4; + exec.DR1 = exec.DR4 = 0; + exec.num_cliprects = 0; + exec.cliprects_ptr = 0; + exec.flags = HAS_BLT_RING(intel_get_drm_devid(fd)) ? I915_EXEC_BLT : 0; + i915_execbuffer2_set_context_id(exec, 0); + exec.rsvd2 = 0; + + gem_execbuf(fd, &exec); + + gem_sync(fd, handle); + gem_close(fd, handle); +} + +static bool area_ok(uint32_t *p, const int start, + const int size, const uint32_t sval) +{ + int i; + + for (i = start; i < start + size; i++) + if (p[i] != i - start + sval) { + igt_info("%d: 0x%08x differs from assumed 0x%08x\n", + i, p[i], i + sval); + return false; + } + + return true; +} + +static void +_test_destination_align(int fd, + const uint32_t dst_align, const uint32_t src_align, + const uint32_t w, const uint32_t h) +{ + const uint32_t size = sizeof(linear) / 4; + const uint32_t guard_val = 0xdeadf00d; + const int copy_len = h * w; + const int src_len = copy_len + src_align; + const int dst_tail = 2 * 16 + 3; + const int dst_total = dst_align + src_len + dst_tail; + uint32_t *p; + uint32_t h_dst; + uint32_t h_src; + int i; + + igt_assert(src_len < size); + p = linear; + + h_src = gem_create(fd, src_len * 4); + igt_assert(h_src != 0); + + for (i = 0; i < src_len; i++) + p[i] = i; + + gem_write(fd, h_src, 0, p, src_len * 4); + gem_read(fd, h_src, 0, p, src_len * 4); + igt_assert(area_ok(p, 0, src_len, 0)); + + h_dst = gem_create(fd, dst_total * 4); + igt_assert(h_dst != 0); + + for (i = 0; i < dst_total; i++) + p[i] = guard_val + i; + + gem_write(fd, h_dst, 0, p, dst_total * 4); + gem_read(fd, h_dst, 0, p, dst_total * 4); + + igt_assert(area_ok(p, 0, dst_total, guard_val)); + + copy_align(fd, h_dst, dst_align, h_src, src_align, w, h); + gem_read(fd, h_dst, 0, p, dst_total * 4); + + igt_assert(area_ok(p, 0, dst_align, guard_val)); + igt_assert(area_ok(p, dst_align, copy_len, src_align)); + igt_assert(area_ok(p, copy_len + dst_align, + dst_total - copy_len - dst_align, + guard_val + copy_len + dst_align)); + + gem_close(fd, h_src); + gem_close(fd, h_dst); +} + +static void test_destination_align(int fd, + int dst_align, int src_align, + int max_w, int max_h) +{ + int i, j, w, h; + + for (i = 0; i <= src_align; i++) + for (j = 0; j <= dst_align; j++) + for (h = 1; h <= max_h; h ++) + for (w = 1; w <= max_w; w++) + _test_destination_align(fd, j, i, w, h); +} + +igt_simple_main +{ + int fd = -1; + + igt_skip_on_simulation(); + + igt_fixture { + fd = drm_open_any(); + igt_assert(fd >= 0); + + gen = intel_gen(intel_get_drm_devid(fd)); + } + + test_destination_align(fd, 17, 17, 17, 17); +}