| Message ID | 1418675206-17499-1-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +4-4 360/366 360/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT 289/289 289/289
HSW 563/564 563/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*ILK igt_kms_pipe_crc_basic_bad-source PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_setmode_invalid-clone-exclusive-crtc PASS(2, M26) DMESG_WARN(1, M26)
*ILK igt_kms_flip_rcs-wf_vblank-vs-dpms-interruptible PASS(2, M26) DMESG_WARN(1, M26)
ILK igt_drv_suspend_fence-restore-untiled DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_bcs-flip-vs-modeset-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_busy-flip-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
ILK igt_kms_flip_flip-vs-rmfb-interruptible DMESG_WARN(1, M26)PASS(5, M37M26) PASS(1, M26)
*ILK igt_kms_flip_wf_vblank-vs-modeset-interruptible PASS(2, M26) DMESG_WARN(1, M26)
Note: You need to pay more attention to line start with '*'
On Mon, Dec 15, 2014 at 12:26:46PM -0800, Ben Widawsky wrote: > From: Ben Widawsky <ben@bwidawsk.net> > > When the original drm code was written there were no centralized functions for > doing a coordinated wbinvd across all CPUs. Now (since 2010) there are, so use > them instead of rolling a new one. > > v2: On x86 UP systems the wbinvd_on_all_cpus() is defined as a static inline in > smp.h. We must therefore include this file so we don't get compiler errors. > This error was found by 0-DAY kernel test infrastructure. We only need this for > x86. Oh dear UP ;-) Thanks for the quick updated, new patch merged to dinq. -Daniel > > Cc: Intel GFX <intel-gfx@lists.freedesktop.org> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) > --- > drivers/gpu/drm/drm_cache.c | 13 ++++--------- > 1 file changed, 4 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c > index a6b6906..9a62d7a 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -32,6 +32,7 @@ > #include <drm/drmP.h> > > #if defined(CONFIG_X86) > +#include <asm/smp.h> > > /* > * clflushopt is an unordered instruction which needs fencing with mfence or > @@ -64,12 +65,6 @@ static void drm_cache_flush_clflush(struct page *pages[], > drm_clflush_page(*pages++); > mb(); > } > - > -static void > -drm_clflush_ipi_handler(void *null) > -{ > - wbinvd(); > -} > #endif > > void > @@ -82,7 +77,7 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) > return; > } > > - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) > + if (wbinvd_on_all_cpus()) > printk(KERN_ERR "Timed out waiting for cache flush.\n"); > > #elif defined(__powerpc__) > @@ -121,7 +116,7 @@ drm_clflush_sg(struct sg_table *st) > return; > } > > - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) > + if (wbinvd_on_all_cpus()) > printk(KERN_ERR "Timed out waiting for cache flush.\n"); > #else > printk(KERN_ERR "Architecture has no drm_cache.c support\n"); > @@ -144,7 +139,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) > return; > } > > - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) > + if (wbinvd_on_all_cpus()) > printk(KERN_ERR "Timed out waiting for cache flush.\n"); > #else > printk(KERN_ERR "Architecture has no drm_cache.c support\n"); > -- > 2.1.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index a6b6906..9a62d7a 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -32,6 +32,7 @@ #include <drm/drmP.h> #if defined(CONFIG_X86) +#include <asm/smp.h> /* * clflushopt is an unordered instruction which needs fencing with mfence or @@ -64,12 +65,6 @@ static void drm_cache_flush_clflush(struct page *pages[], drm_clflush_page(*pages++); mb(); } - -static void -drm_clflush_ipi_handler(void *null) -{ - wbinvd(); -} #endif void @@ -82,7 +77,7 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) return; } - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + if (wbinvd_on_all_cpus()) printk(KERN_ERR "Timed out waiting for cache flush.\n"); #elif defined(__powerpc__) @@ -121,7 +116,7 @@ drm_clflush_sg(struct sg_table *st) return; } - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + if (wbinvd_on_all_cpus()) printk(KERN_ERR "Timed out waiting for cache flush.\n"); #else printk(KERN_ERR "Architecture has no drm_cache.c support\n"); @@ -144,7 +139,7 @@ drm_clflush_virt_range(void *addr, unsigned long length) return; } - if (on_each_cpu(drm_clflush_ipi_handler, NULL, 1) != 0) + if (wbinvd_on_all_cpus()) printk(KERN_ERR "Timed out waiting for cache flush.\n"); #else printk(KERN_ERR "Architecture has no drm_cache.c support\n");