From patchwork Thu Dec 18 17:41:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 5515511 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B114EBEEA8 for ; Thu, 18 Dec 2014 17:32:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CDEF6208F3 for ; Thu, 18 Dec 2014 17:32:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E8821208EE for ; Thu, 18 Dec 2014 17:32:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 79C7B6EA3B; Thu, 18 Dec 2014 09:32:42 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AECE6EA37 for ; Thu, 18 Dec 2014 09:32:41 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 18 Dec 2014 09:24:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,601,1413270000"; d="scan'208";a="639829569" Received: from jeffdesk.fso.intel.com ([10.5.53.102]) by fmsmga001.fm.intel.com with ESMTP; 18 Dec 2014 09:24:39 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Dec 2014 11:41:54 -0600 Message-Id: <1418924516-10418-2-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.2.0 In-Reply-To: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> References: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Export GT config attributes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee Setup new I915_GETPARAM ioctl entries for slice total, subslice total, EU total, and threads per EU, so that userspace can query the kernel for the values of these attributes instead of maintaining individual lookup tables which must be indexed by PCI ID. The motivation for this change is that fusing can be used to create multiple slice, subslice, and EU configuration within the same PCI ID. CHV is the first such device to do this and thus make an ID-based lookup table approach unreliable. The best solution is for the kernel to determine the precise config from fuse registers and share the required information with userspace. Moving to this approach has the added benefit of reducing the number of static parameters that userspace must maintain for current and future devices. The kernel detection of these values is device-specific and not included in this patch. Because zero is not a valid value for any of these parameters, a value of zero is interpreted as unknown for the device. For: VIZ-4636 Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 5 +++++ include/uapi/drm/i915_drm.h | 4 ++++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 52730ed..a6634e6 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -143,6 +143,26 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_COHERENT_PHYS_GTT: value = 1; break; + case I915_PARAM_SLICE_TOTAL: + value = INTEL_INFO(dev)->slice_total; + if (!value) + return -ENODEV; + break; + case I915_PARAM_SUBSLICE_TOTAL: + value = INTEL_INFO(dev)->subslice_total; + if (!value) + return -ENODEV; + break; + case I915_PARAM_EU_TOTAL: + value = INTEL_INFO(dev)->eu_total; + if (!value) + return -ENODEV; + break; + case I915_PARAM_THREADS_PER_EU: + value = INTEL_INFO(dev)->threads_per_eu; + if (!value) + return -ENODEV; + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 921e4c5..02afb29 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -653,6 +653,11 @@ struct intel_device_info { int trans_offsets[I915_MAX_TRANSCODERS]; int palette_offsets[I915_MAX_PIPES]; int cursor_offsets[I915_MAX_PIPES]; + + unsigned int slice_total; + unsigned int subslice_total; + unsigned int eu_total; + unsigned int threads_per_eu; }; #undef DEFINE_FLAG diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 2502622..5fd37b9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -341,6 +341,10 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_WT 27 #define I915_PARAM_CMD_PARSER_VERSION 28 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 +#define I915_PARAM_SLICE_TOTAL 30 +#define I915_PARAM_SUBSLICE_TOTAL 31 +#define I915_PARAM_EU_TOTAL 32 +#define I915_PARAM_THREADS_PER_EU 33 typedef struct drm_i915_getparam { int param;