From patchwork Thu Dec 18 17:41:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 5515521 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B02789F1CD for ; Thu, 18 Dec 2014 17:32:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E2BE1208EE for ; Thu, 18 Dec 2014 17:32:44 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 027E3209A7 for ; Thu, 18 Dec 2014 17:32:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E2A66EA5D; Thu, 18 Dec 2014 09:32:43 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id C986F6EA37 for ; Thu, 18 Dec 2014 09:32:41 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 18 Dec 2014 09:24:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,601,1413270000"; d="scan'208";a="639829580" Received: from jeffdesk.fso.intel.com ([10.5.53.102]) by fmsmga001.fm.intel.com with ESMTP; 18 Dec 2014 09:24:40 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Dec 2014 11:41:55 -0600 Message-Id: <1418924516-10418-3-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.2.0 In-Reply-To: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> References: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 2/3] drm/i915/chv: Determine CHV GT config attributes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee Cherryview fusing allows for different EU totals within a single device ID, so fused-based detection is a must. Go ahead and determine subslice total from fuse as well just in case. Slice total and threads per EU are fixed for all CHV. For: VIZ-4636 Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index a6634e6..0ab8f3a 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -618,6 +618,24 @@ static void intel_device_info_runtime_init(struct drm_device *dev) info->num_pipes = 0; } } + + /* Initialize required GT attributes info */ + if (IS_CHERRYVIEW(dev)) { + u32 reg, ss_dis, eu_dis; + + reg = I915_READ(CHV_FUSE_GT); + ss_dis = reg & (CHV_FGT_DISABLE_SS0 | + CHV_FGT_DISABLE_SS1); + eu_dis = reg & (CHV_FGT_EU_DIS_SS0_R0_MASK | + CHV_FGT_EU_DIS_SS0_R1_MASK | + CHV_FGT_EU_DIS_SS1_R0_MASK | + CHV_FGT_EU_DIS_SS1_R1_MASK); + + info->slice_total = 1; + info->subslice_total = 2 - hweight32(ss_dis); + info->eu_total = 16 - hweight32(eu_dis); + info->threads_per_eu = 7; + } } /** diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 40ca873..f60119c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6127,6 +6127,19 @@ enum punit_power_well { #define GEN7_MISCCPCTL (0x9424) #define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0) +/* Fuse readout registers for GT */ +#define CHV_FUSE_GT 0x182168 +#define CHV_FGT_DISABLE_SS0 10 +#define CHV_FGT_DISABLE_SS1 11 +#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 +#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 +#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 +#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) +#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 +#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) + /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */