From patchwork Thu Dec 18 17:41:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 5515531 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6A0CBBEEA8 for ; Thu, 18 Dec 2014 17:32:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 97736208F3 for ; Thu, 18 Dec 2014 17:32:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A7ABC209A9 for ; Thu, 18 Dec 2014 17:32:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C84906EA60; Thu, 18 Dec 2014 09:32:43 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 675466EA37 for ; Thu, 18 Dec 2014 09:32:42 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 18 Dec 2014 09:24:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,601,1413270000"; d="scan'208";a="639829592" Received: from jeffdesk.fso.intel.com ([10.5.53.102]) by fmsmga001.fm.intel.com with ESMTP; 18 Dec 2014 09:24:41 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 18 Dec 2014 11:41:56 -0600 Message-Id: <1418924516-10418-4-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.2.0 In-Reply-To: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> References: <1418924516-10418-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 3/3] drm/i915/bdw: Determine BDW GT config attributes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee Broadwell values could be tabulated by device ID, but we go ahead and detect from fuses because it is easier and more flexible. For: VIZ-4636 Signed-off-by: Jeff McGee --- drivers/gpu/drm/i915/i915_dma.c | 20 +++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 0ab8f3a..023d010 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -620,7 +620,25 @@ static void intel_device_info_runtime_init(struct drm_device *dev) } /* Initialize required GT attributes info */ - if (IS_CHERRYVIEW(dev)) { + if (IS_BROADWELL(dev)) { + u32 fuse2, eu_dis0, eu_dis1, eu_dis2, s_ena, ss_dis; + + fuse2 = I915_READ(GEN8_FUSE2); + eu_dis0 = I915_READ(GEN8_EU_DISABLE0); + eu_dis1 = I915_READ(GEN8_EU_DISABLE1); + eu_dis2 = I915_READ(GEN8_EU_DISABLE2); + s_ena = fuse2 & GEN8_F2_S_ENA_MASK; + ss_dis = fuse2 & GEN8_F2_SS_DIS_MASK; + eu_dis2 &= GEN8_EU_DIS2_S2_SS2_MASK; + + info->slice_total = hweight32(s_ena); + info->subslice_total = (3 - hweight32(ss_dis)) * + info->slice_total; + info->eu_total = 72 - (hweight32(eu_dis0) + + hweight32(eu_dis1) + + hweight32(eu_dis2)); + info->threads_per_eu = 7; + } else if (IS_CHERRYVIEW(dev)) { u32 reg, ss_dis, eu_dis; reg = I915_READ(CHV_FUSE_GT); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f60119c..b08747c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6140,6 +6140,17 @@ enum punit_power_well { #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) +#define GEN8_FUSE2 0x9120 +#define GEN8_F2_SS_DIS_SHIFT 21 +#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) +#define GEN8_F2_S_ENA_SHIFT 25 +#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) + +#define GEN8_EU_DISABLE0 0x9134 +#define GEN8_EU_DISABLE1 0x9138 +#define GEN8_EU_DISABLE2 0x913c +#define GEN8_EU_DIS2_S2_SS2_MASK (0xff) + /* IVYBRIDGE DPF */ #define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */ #define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */