From patchwork Fri Dec 19 02:20:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 5517101 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 825E1BEEA8 for ; Fri, 19 Dec 2014 02:20:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A35CB2011E for ; Fri, 19 Dec 2014 02:20:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BA6EF2011B for ; Fri, 19 Dec 2014 02:20:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5A9DD6EAD4; Thu, 18 Dec 2014 18:20:22 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id EDA046EAD4 for ; Thu, 18 Dec 2014 18:20:20 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 18 Dec 2014 18:17:58 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,604,1413270000"; d="scan'208";a="626339137" Received: from statham.jf.intel.com ([10.7.198.95]) by orsmga001.jf.intel.com with ESMTP; 18 Dec 2014 18:20:20 -0800 From: Ben Widawsky To: Intel GFX Date: Thu, 18 Dec 2014 18:20:18 -0800 Message-Id: <1418955618-382-1-git-send-email-benjamin.widawsky@intel.com> X-Mailer: git-send-email 2.2.0 MIME-Version: 1.0 Cc: Ben Widawsky , stable@vger.kernel.org Subject: [Intel-gfx] [PATCH] drm/i915/hsw: Implement Selective Write workaround X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky The docs specify this needs to be set on HSW GT1 parts. I've implemented it as such since it should only be needed when using RC6, but it can probably go anywhere. This patch fixes extremely reproducible hangs on our Jenkins setup. The interesting failure signature is: IPEHR: 0x780c0000 (3DSTATE_VF) INSTDONE_0: 0xffdfbffa (SVG + VS) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87138 (more?) Cc: Kenneth Graunke Cc: stable@vger.kernel.org Reported-by: Mark Janes Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 7 +++++++ drivers/gpu/drm/i915/intel_pm.c | 9 +++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 921e4c5..f69984d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2282,6 +2282,8 @@ struct drm_i915_cmd_table { (INTEL_DEVID(dev) & 0xf) == 0xe)) #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ (INTEL_DEVID(dev) & 0x00F0) == 0x0020) +#define IS_HSW_GT1(dev) (IS_HASWELL(dev) && \ + (INTEL_DEVID(dev) & 0x00F0) == 0x0) #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 40ca873..f9ff662 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1218,6 +1218,13 @@ enum punit_power_well { #define RING_DMA_FADD_UDW(base) ((base)+0x60) /* gen8+ */ #define RING_INSTPM(base) ((base)+0xc0) #define RING_MI_MODE(base) ((base)+0x9c) +#define RING_WAIT_FOR_RC6_EXIT(base) ((base)+0xcc) +#define RING_RC6_SEL_WRITE_ADDR_MASK (0x7 << 4) +#define RING_RC6_SEL_WRITE_ADDR_MULTICAST (0x0 << 4) +#define RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT (0x4 << 4) +#define RING_RC6_SEL_WRITE_ADDR_UPPER_RIGHT (0x5 << 4) +#define RING_RC6_SEL_WRITE_ADDR_LOWER_LEFT (0x6 << 4) +#define RING_RC6_SEL_WRITE_ADDR_LOWER_RIGHT (0x7 << 4) #define INSTPS 0x02070 /* 965+ only */ #define INSTDONE1 0x0207c /* 965+ only */ #define ACTHD_I965 0x02074 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a3ebaa8..a27003c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4259,6 +4259,15 @@ static void gen6_enable_rps(struct drm_device *dev) DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); } + /* HSW GT1: "This field must be always [be] programmed to “100” , this + * is required to address know [sic] HW issue." */ + if (IS_HSW_GT1(dev)) { + for_each_ring(ring, dev_priv, i) { + I915_WRITE(RING_WAIT_FOR_RC6_EXIT(ring->mmio_base), + _MASKED_FIELD(RING_RC6_SEL_WRITE_ADDR_MASK, + RING_RC6_SEL_WRITE_ADDR_UPPER_LEFT)); + } + } gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); }