diff mbox

[v2] drm/i915: Reset CSB read pointer in ring init

Message ID 1420801777-26343-1-git-send-email-thomas.daniel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Thomas Daniel Jan. 9, 2015, 11:09 a.m. UTC 
A previous commit enabled execlists by default:

       commit 27401d126b5b ("drm/i915/bdw: Enable execlists by default where supported")

This allowed routine testing of execlists which exposed a regression when
resuming from suspend.  The cause was tracked down the to recent changes to the
ring init sequence:

       commit 35a57ffbb108 ("drm/i915: Only init engines once")

During a suspend/resume cycle the hardware Context Status Buffer write pointer
is reset.  However since the recent changes to the init sequence the software CSB
read pointer is no longer reset.  This means that context status events are not
handled correctly and new contexts are not written to the ELSP, resulting in an
apparent GPU hang.

Pending further changes to the ring init code, just move the
ring->next_context_status_buffer initialization into gen8_init_common_ring to
fix this regression.

v2: Moved init into gen8_init_common_ring rather than context_enable after
feedback from Daniel Vetter.  Updated commit msg to reflect this and also cite
commits related to the regression.  Fixed bz link to correct bug.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Shuang He Jan. 9, 2015, 4:31 p.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -31              363/364              332/364
ILK                 -20              364/366              344/366
SNB              +4-65              443/450              382/450
IVB                 -44              496/498              452/498
BYT                 -8              288/289              280/289
HSW              +5-46              542/564              501/564
BDW                 -33              415/417              382/417
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(7, M23M25)PASS(1, M25)      NSPT(1, M23)
 PNV  igt_gem_pread_after_blit_interruptible      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_normal      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_normal-display      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 PNV  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M23M25)PASS(1, M25)      NRUN(1, M23)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(7, M26M37)PASS(1, M37)      NSPT(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-display      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 ILK  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M26M37)PASS(1, M37)      NRUN(1, M37)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(7, M22M35)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-display      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-snoop      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_interruptible-uncached      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-display      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-snoop      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_gem_pread_after_blit_normal-uncached      NRUN(3, M22M35)PASS(1, M35)      NRUN(1, M35)
 SNB  igt_kms_cursor_crc_cursor-size-change      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race      DMESG_WARN(3, M35M22)PASS(6, M35M22)      PASS(1, M35)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(2, M35M22)PASS(7, M35M22)      PASS(1, M35)
 SNB  igt_kms_flip_event_leak      NSPT(5, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_flip_modeset-vs-vblank-race      DMESG_WARN(4, M35M22)PASS(6, M35M22)      PASS(1, M35)
*SNB  igt_kms_flip_nonexisting-fb      PASS(2, M35)      NSPT(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_plane_plane-position-hole-pipe-B-plane-1      DMESG_WARN(1, M35)PASS(10, M35M22)      PASS(1, M35)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_cursor      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_fences      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_fences-dpms      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_gem-pread      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_i2c      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 SNB  igt_pm_rpm_rte      NSPT(6, M35M22)PASS(1, M35)      NSPT(1, M35)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
 IVB  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(7, M21M34M4)PASS(1, M34)      NSPT(1, M34)
*IVB  igt_gem_pread_after_blit_interruptible      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_normal      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_normal-display      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*IVB  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M21M4)PASS(1, M34)      NRUN(1, M34)
*BYT  igt_gem_pread_after_blit_interruptible      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_normal      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_normal-display      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
*BYT  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M51)PASS(1, M48)      NRUN(1, M48)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-forked      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
 HSW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(6, M19M20M40)PASS(1, M40)      NSPT(1, M40)
*HSW  igt_gem_pread_after_blit_interruptible      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_normal      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_normal-display      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M19)PASS(1, M40)      NRUN(1, M40)
*HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset      DMESG_WARN(1, M40)PASS(5, M19M20)      PASS(1, M40)
*HSW  igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40M19)PASS(5, M19M20)      PASS(1, M40)
*HSW  igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset-interruptible      DMESG_WARN(2, M40)PASS(6, M19M20)      PASS(1, M40)
 HSW  igt_kms_plane_plane-panning-bottom-right-pipe-C-plane-1      TIMEOUT(3, M40)PASS(7, M19M40M20)      PASS(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-A-plane-2      PASS(1, M40)      TIMEOUT(1, M40)
*HSW  igt_kms_plane_plane-panning-top-left-pipe-B-plane-1      PASS(1, M40)      DMESG_FAIL(1, M40)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(4, M19)DMESG_WARN(1, M40)PASS(5, M40M20)      PASS(1, M40)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-early-read-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-gpu-read-after-write-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-bcs-overwrite-source-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-early-read-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-gpu-read-after-write-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpu-rcs-overwrite-source-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-early-read-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-gpu-read-after-write-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-early-read-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-gpu-read-after-write-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_concurrent_blit_gpuX-rcs-overwrite-source-interruptible      NSPT(7, M28M30)PASS(1, M30)      NSPT(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-display      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-snoop      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_interruptible-uncached      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-display      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-snoop      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
 BDW  igt_gem_pread_after_blit_normal-uncached      NRUN(2, M28M30)PASS(1, M30)      NRUN(1, M30)
*BDW  igt_gem_multi_bsd_sync_loop      PASS(6, M30M28)      DMESG_WARN(1, M30)
Note: You need to pay more attention to line start with '*'
Dave Gordon Jan. 9, 2015, 4:54 p.m. UTC | #2 
On 09/01/15 11:09, Daniel, Thomas wrote:
> A previous commit enabled execlists by default:
> 
>        commit 27401d126b5b ("drm/i915/bdw: Enable execlists by default where supported")
> 
> This allowed routine testing of execlists which exposed a regression when
> resuming from suspend.  The cause was tracked down the to recent changes to the
> ring init sequence:
> 
>        commit 35a57ffbb108 ("drm/i915: Only init engines once")
> 
> During a suspend/resume cycle the hardware Context Status Buffer write pointer
> is reset.  However since the recent changes to the init sequence the software CSB
> read pointer is no longer reset.  This means that context status events are not
> handled correctly and new contexts are not written to the ELSP, resulting in an
> apparent GPU hang.
> 
> Pending further changes to the ring init code, just move the
> ring->next_context_status_buffer initialization into gen8_init_common_ring to
> fix this regression.
> 
> v2: Moved init into gen8_init_common_ring rather than context_enable after
> feedback from Daniel Vetter.  Updated commit msg to reflect this and also cite
> commits related to the regression.  Fixed bz link to correct bug.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88096
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
> Cc: Dave Gordon <david.s.gordon@intel.com>
> Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 7670a0f..e405b61 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1137,6 +1137,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring)
>  		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
>  		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>  	POSTING_READ(RING_MODE_GEN7(ring));
> +	ring->next_context_status_buffer = 0;
>  	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
>  
>  	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
> @@ -1394,7 +1395,6 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
>  	INIT_LIST_HEAD(&ring->execlist_queue);
>  	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
>  	spin_lock_init(&ring->execlist_lock);
> -	ring->next_context_status_buffer = 0;
>  
>  	ret = i915_cmd_parser_init_ring(ring);
>  	if (ret)
> 

LGTM.
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7670a0f..e405b61 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1137,6 +1137,7 @@  static int gen8_init_common_ring(struct intel_engine_cs *ring)
 		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
 		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
 	POSTING_READ(RING_MODE_GEN7(ring));
+	ring->next_context_status_buffer = 0;
 	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name);
 
 	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
@@ -1394,7 +1395,6 @@  static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
 	INIT_LIST_HEAD(&ring->execlist_queue);
 	INIT_LIST_HEAD(&ring->execlist_retired_req_list);
 	spin_lock_init(&ring->execlist_lock);
-	ring->next_context_status_buffer = 0;
 
 	ret = i915_cmd_parser_init_ring(ring);
 	if (ret)