From patchwork Tue Jan 13 11:52:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 5619691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C5658C058E for ; Tue, 13 Jan 2015 11:52:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 02406205DD for ; Tue, 13 Jan 2015 11:52:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BA18420614 for ; Tue, 13 Jan 2015 11:52:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C943E6E5DE; Tue, 13 Jan 2015 03:52:31 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DF046E5D7 for ; Tue, 13 Jan 2015 03:52:30 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 13 Jan 2015 03:47:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,749,1413270000"; d="scan'208";a="661060018" Received: from michelth-linux.isw.intel.com ([10.102.226.150]) by fmsmga002.fm.intel.com with ESMTP; 13 Jan 2015 03:52:29 -0800 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jan 2015 11:52:30 +0000 Message-Id: <1421149959-30383-17-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1421149959-30383-1-git-send-email-michel.thierry@intel.com> References: <1418922621-25818-1-git-send-email-michel.thierry@intel.com> <1421149959-30383-1-git-send-email-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v3 16/25] drm/i915/bdw: Use dynamic allocation idioms on free X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky The page directory freer is left here for now as it's still useful given that GEN8 still preallocates. Once the allocation functions are broken up into more discrete chunks, we'll follow suit and destroy this leftover piece. v2: Match trace_i915_va_teardown params v3: Multiple rebases. v4: Updated to use unmap_and_free_pt. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry (v2+) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 54 +++++++++++++++++++++++-------------- drivers/gpu/drm/i915/i915_gem_gtt.h | 46 +++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 40996fe..756907f 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -580,27 +580,32 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, } } -static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) +static void gen8_teardown_va_range(struct i915_address_space *vm, + uint64_t start, uint64_t length) { - int i; - - if (!pd->page) - return; - - for (i = 0; i < GEN8_PDES_PER_PAGE; i++) { - unmap_and_free_pt(pd->page_tables[i], dev); - pd->page_tables[i] = NULL; + struct i915_hw_ppgtt *ppgtt = + container_of(vm, struct i915_hw_ppgtt, base); + struct i915_page_directory_entry *pd; + struct i915_page_table_entry *pt; + uint64_t temp; + uint32_t pdpe, pde; + + gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { + uint64_t pd_len = gen8_clamp_pd(start, length); + uint64_t pd_start = start; + gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { + unmap_and_free_pt(pt, vm->dev); + } + unmap_and_free_pd(pd); } } -static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +/* This function will die soon */ +static void gen8_free_full_page_directory(struct i915_hw_ppgtt *ppgtt, int i) { - int i; - - for (i = 0; i < ppgtt->num_pd_pages; i++) { - gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); - unmap_and_free_pd(ppgtt->pdp.page_directory[i]); - } + gen8_teardown_va_range(&ppgtt->base, + i << GEN8_PDPE_SHIFT, + (1 << GEN8_PDPE_SHIFT)); } static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) @@ -615,19 +620,28 @@ static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) continue; pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); + PCI_DMA_BIDIRECTIONAL); for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; - struct i915_page_table_entry *pt = pd->page_tables[j]; + struct i915_page_table_entry *pt = pd->page_tables[j]; dma_addr_t addr = pt->daddr; if (addr) pci_unmap_page(hwdev, addr, PAGE_SIZE, - PCI_DMA_BIDIRECTIONAL); + PCI_DMA_BIDIRECTIONAL); } } } +static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) +{ + trace_i915_va_teardown(&ppgtt->base, + ppgtt->base.start, ppgtt->base.total, + VM_TO_TRACE_NAME(&ppgtt->base)); + gen8_teardown_va_range(&ppgtt->base, + ppgtt->base.start, ppgtt->base.total); +} + static void gen8_ppgtt_cleanup(struct i915_address_space *vm) { struct i915_hw_ppgtt *ppgtt = @@ -652,7 +666,7 @@ static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) unwind_out: while (i--) - gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); + gen8_free_full_page_directory(ppgtt, i); return -ENOMEM; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 074b368..c82a029 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -385,6 +385,52 @@ static inline uint32_t gen6_pde_index(uint32_t addr) return i915_pde_index(addr, GEN6_PDE_SHIFT); } +#define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ + for (iter = gen8_pde_index(start), pt = (pd)->page_tables[iter]; \ + length > 0 && iter < GEN8_PDES_PER_PAGE; \ + pt = (pd)->page_tables[++iter], \ + temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +#define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ + for (iter = gen8_pdpe_index(start), pd = (pdp)->page_directory[iter]; \ + length > 0 && iter < GEN8_LEGACY_PDPES; \ + pd = (pdp)->page_directory[++iter], \ + temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ + temp = min(temp, length), \ + start += temp, length -= temp) + +/* Clamp length to the next page_directory boundary */ +static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) +{ + uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); + if (next_pd > (start + length)) + return length; + + return next_pd - start; +} + +static inline uint32_t gen8_pte_index(uint64_t address) +{ + return i915_pte_index(address, GEN8_PDE_SHIFT); +} + +static inline uint32_t gen8_pde_index(uint64_t address) +{ + return i915_pde_index(address, GEN8_PDE_SHIFT); +} + +static inline uint32_t gen8_pdpe_index(uint64_t address) +{ + return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; +} + +static inline uint32_t gen8_pml4e_index(uint64_t address) +{ + BUG(); /* For 64B */ +} + int i915_gem_gtt_init(struct drm_device *dev); void i915_gem_init_global_gtt(struct drm_device *dev); void i915_global_gtt_cleanup(struct drm_device *dev);