| Message ID | 1421431648-22904-2-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Damien Lespiau <damien.lespiau@intel.com> writes: > From: Jesse Barnes <jbarnes@virtuousgeek.org> > > Per latest PM programming guide. > > v2: the wrong flavour of the function updating the ring frequency was > called, leading to dead locks (Tvrtko) > > v3: Add GEN6_RP_MEDIA_IS_GFX to RP_CONTROL (Imre, done by Damien) > > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 03fc7f2..3a0aec0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4025,9 +4025,37 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) > } > } > > +/* See the Gen9_GT_PM_Programming_Guide doc for the below */ > static void gen9_enable_rps(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > + > + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); > + > + I915_WRITE(GEN6_RPNSWREQ, 0xc800000); > + I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); > + > + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); > + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); > + I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); > + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); > + I915_WRITE(GEN6_RP_UP_EI, 0x101d0); > + I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); > + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); > + I915_WRITE(GEN6_PMINTRMSK, 0x6); > + I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | > + GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | > + GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | > + GEN6_RP_DOWN_IDLE_AVG); > + > + gen6_enable_rps_interrupts(dev); > + > + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); > +} > + > +static void gen9_enable_rc6(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_engine_cs *ring; > uint32_t rc6_mask = 0; > int unused; > @@ -5527,7 +5555,9 @@ static void intel_gen6_powersave_work(struct work_struct *work) > } else if (IS_VALLEYVIEW(dev)) { > valleyview_enable_rps(dev); > } else if (INTEL_INFO(dev)->gen >= 9) { > + gen9_enable_rc6(dev); > gen9_enable_rps(dev); > + __gen6_update_ring_freq(dev); > } else if (IS_BROADWELL(dev)) { > gen8_enable_rps(dev); > __gen6_update_ring_freq(dev); > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 03fc7f2..3a0aec0 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4025,9 +4025,37 @@ static void gen6_init_rps_frequencies(struct drm_device *dev) } } +/* See the Gen9_GT_PM_Programming_Guide doc for the below */ static void gen9_enable_rps(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + + gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); + + I915_WRITE(GEN6_RPNSWREQ, 0xc800000); + I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); + + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); + I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); + I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); + I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); + I915_WRITE(GEN6_RP_UP_EI, 0x101d0); + I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); + I915_WRITE(GEN6_PMINTRMSK, 0x6); + I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | + GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | + GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | + GEN6_RP_DOWN_IDLE_AVG); + + gen6_enable_rps_interrupts(dev); + + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); +} + +static void gen9_enable_rc6(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *ring; uint32_t rc6_mask = 0; int unused; @@ -5527,7 +5555,9 @@ static void intel_gen6_powersave_work(struct work_struct *work) } else if (IS_VALLEYVIEW(dev)) { valleyview_enable_rps(dev); } else if (INTEL_INFO(dev)->gen >= 9) { + gen9_enable_rc6(dev); gen9_enable_rps(dev); + __gen6_update_ring_freq(dev); } else if (IS_BROADWELL(dev)) { gen8_enable_rps(dev); __gen6_update_ring_freq(dev);