From patchwork Fri Jan 16 18:07:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lespiau, Damien" X-Patchwork-Id: 5649881 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 246A49F2ED for ; Fri, 16 Jan 2015 18:07:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A992202F0 for ; Fri, 16 Jan 2015 18:07:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 68D7F202E9 for ; Fri, 16 Jan 2015 18:07:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A8F56E867; Fri, 16 Jan 2015 10:07:40 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 022D96E867 for ; Fri, 16 Jan 2015 10:07:36 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 16 Jan 2015 10:04:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,412,1418112000"; d="scan'208";a="671181071" Received: from slahti-mobl1.ger.corp.intel.com (HELO strange.ger.corp.intel.com) ([10.252.1.140]) by orsmga002.jf.intel.com with ESMTP; 16 Jan 2015 10:07:33 -0800 From: Damien Lespiau To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Jan 2015 18:07:27 +0000 Message-Id: <1421431648-22904-4-git-send-email-damien.lespiau@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1421431648-22904-1-git-send-email-damien.lespiau@intel.com> References: <1421431648-22904-1-git-send-email-damien.lespiau@intel.com> Subject: [Intel-gfx] [PATCH 3/4] drm/i915/skl: Gen9 coarse power gating X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Zhe Wang Enable coarse power gating for Gen9. This feature allows render and media engine to enter RC6 independently. Policies are configured together with RC6. This feature will only be enabled when RC6 is enabled. Signed-off-by: Zhe Wang Signed-off-by: Damien Lespiau Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cb96041..3d08f9d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6065,6 +6065,9 @@ enum skl_disp_power_wells { #define GEN6_PMINTRMSK 0xA168 #define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) #define VLV_PWRDWNUPCTL 0xA294 +#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4 +#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8 +#define GEN9_PG_ENABLE 0xA210 #define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) #define PIXEL_OVERLAP_CNT_MASK (3 << 30) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f40b8f2..71bf4f4 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3892,6 +3892,7 @@ static void gen9_disable_rps(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; I915_WRITE(GEN6_RC_CONTROL, 0); + I915_WRITE(GEN9_PG_ENABLE, 0); } static void gen6_disable_rps(struct drm_device *dev) @@ -4081,6 +4082,10 @@ static void gen9_enable_rc6(struct drm_device *dev) I915_WRITE(GEN6_RC_SLEEP, 0); I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ + /* 2c: Program Coarse Power Gating Policies. */ + I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); + I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); + /* 3a: Enable RC6 */ if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) rc6_mask = GEN6_RC_CTL_RC6_ENABLE; @@ -4090,6 +4095,9 @@ static void gen9_enable_rc6(struct drm_device *dev) GEN6_RC_CTL_EI_MODE(1) | rc6_mask); + /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ + I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); + gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); }