diff mbox

[9/9] drm/i915: Rename plane_config to initial_plane_config

Message ID 1421693091-18555-10-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien Jan. 19, 2015, 6:44 p.m. UTC
This vfunc and related structure are only used for fast boot, so let's
rename them to not take them as general purpose ones.

Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  6 ++---
 drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_drv.h     |  4 ++--
 drivers/gpu/drm/i915/intel_fbdev.c   |  2 +-
 4 files changed, 33 insertions(+), 23 deletions(-)

Comments

Shuang He Jan. 20, 2015, 3:48 a.m. UTC | #1
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5606
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  353/353              353/353
ILK                                  353/353              353/353
SNB                                  400/422              400/422
IVB                                  487/487              487/487
BYT                                  296/296              296/296
HSW              +21                 487/508              508/508
BDW                                  401/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 HSW  igt_kms_cursor_crc_cursor-size-change      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_kms_fence_pin_leak      NSPT(1, M19)DMESG_WARN(1, M40)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(1, M19)TIMEOUT(1, M40)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_lpsp_non-edp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_cursor      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_cursor-dpms      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_dpms-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_drm-resources-equal      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_fences      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_fences-dpms      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-execbuf      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-mmap-cpu      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-mmap-gtt      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_gem-pread      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_i2c      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_pci-d3-state      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
 HSW  igt_pm_rpm_rte      NSPT(1, M19)PASS(8, M20M19M40)      PASS(1, M19)
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a4d026d..cc2c593 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -504,7 +504,7 @@  struct drm_i915_error_state {
 struct intel_connector;
 struct intel_encoder;
 struct intel_crtc_config;
-struct intel_plane_config;
+struct intel_initial_plane_config;
 struct intel_crtc;
 struct intel_limit;
 struct dpll;
@@ -543,8 +543,8 @@  struct drm_i915_display_funcs {
 	 * fills out the pipe-config with the hw state. */
 	bool (*get_pipe_config)(struct intel_crtc *,
 				struct intel_crtc_config *);
-	void (*get_plane_config)(struct intel_crtc *,
-				 struct intel_plane_config *);
+	void (*get_initial_plane_config)(struct intel_crtc *,
+					 struct intel_initial_plane_config *);
 	int (*crtc_compute_clock)(struct intel_crtc *crtc);
 	void (*crtc_enable)(struct drm_crtc *crtc);
 	void (*crtc_disable)(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 24e74c0..60e99ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2363,8 +2363,9 @@  static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 	}
 }
 
-static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
-				  struct intel_plane_config *plane_config)
+static bool
+intel_alloc_plane_obj(struct intel_crtc *crtc,
+		      struct intel_initial_plane_config *plane_config)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_gem_object *obj = NULL;
@@ -2408,8 +2409,9 @@  out_unref_obj:
 	return false;
 }
 
-static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
-				 struct intel_plane_config *plane_config)
+static void
+intel_find_plane_obj(struct intel_crtc *intel_crtc,
+		     struct intel_initial_plane_config *plane_config)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6566,8 +6568,9 @@  static void vlv_crtc_clock_get(struct intel_crtc *crtc,
 	pipe_config->port_clock = clock.dot / 5;
 }
 
-static void i9xx_get_plane_config(struct intel_crtc *crtc,
-				  struct intel_plane_config *plane_config)
+static void
+i9xx_get_initial_plane_config(struct intel_crtc *crtc,
+			      struct intel_initial_plane_config *plane_config)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7591,8 +7594,9 @@  static void skylake_get_pfit_config(struct intel_crtc *crtc,
 	}
 }
 
-static void skylake_get_plane_config(struct intel_crtc *crtc,
-				      struct intel_plane_config *plane_config)
+static void
+skylake_get_initial_plane_config(struct intel_crtc *crtc,
+				 struct intel_initial_plane_config *plane_config)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7682,8 +7686,9 @@  static void ironlake_get_pfit_config(struct intel_crtc *crtc,
 	}
 }
 
-static void ironlake_get_plane_config(struct intel_crtc *crtc,
-				      struct intel_plane_config *plane_config)
+static void
+ironlake_get_initial_plane_config(struct intel_crtc *crtc,
+				  struct intel_initial_plane_config *plane_config)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -12753,7 +12758,8 @@  static void intel_init_display(struct drm_device *dev)
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
-		dev_priv->display.get_plane_config = skylake_get_plane_config;
+		dev_priv->display.get_initial_plane_config =
+			skylake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -12763,7 +12769,8 @@  static void intel_init_display(struct drm_device *dev)
 			skylake_update_primary_plane;
 	} else if (HAS_DDI(dev)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
-		dev_priv->display.get_plane_config = ironlake_get_plane_config;
+		dev_priv->display.get_initial_plane_config =
+			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
@@ -12773,7 +12780,8 @@  static void intel_init_display(struct drm_device *dev)
 			ironlake_update_primary_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
-		dev_priv->display.get_plane_config = ironlake_get_plane_config;
+		dev_priv->display.get_initial_plane_config =
+			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			ironlake_crtc_compute_clock;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
@@ -12783,7 +12791,8 @@  static void intel_init_display(struct drm_device *dev)
 			ironlake_update_primary_plane;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-		dev_priv->display.get_plane_config = i9xx_get_plane_config;
+		dev_priv->display.get_initial_plane_config =
+			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = valleyview_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -12792,7 +12801,8 @@  static void intel_init_display(struct drm_device *dev)
 			i9xx_update_primary_plane;
 	} else {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-		dev_priv->display.get_plane_config = i9xx_get_plane_config;
+		dev_priv->display.get_initial_plane_config =
+			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = i9xx_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -13164,8 +13174,8 @@  void intel_modeset_init(struct drm_device *dev)
 		 * can even allow for smooth boot transitions if the BIOS
 		 * fb is large enough for the active pipe configuration.
 		 */
-		if (dev_priv->display.get_plane_config) {
-			dev_priv->display.get_plane_config(crtc,
+		if (dev_priv->display.get_initial_plane_config) {
+			dev_priv->display.get_initial_plane_config(crtc,
 							   &crtc->plane_config);
 			/*
 			 * If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0c7f241..cb85509 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -257,7 +257,7 @@  struct intel_plane_state {
 	bool hides_primary;
 };
 
-struct intel_plane_config {
+struct intel_initial_plane_config {
 	unsigned int tiling;
 	int size;
 	u32 base;
@@ -476,7 +476,7 @@  struct intel_crtc {
 	uint32_t cursor_size;
 	uint32_t cursor_base;
 
-	struct intel_plane_config plane_config;
+	struct intel_initial_plane_config plane_config;
 	struct intel_crtc_config config;
 	struct intel_crtc_config *new_config;
 	bool new_enabled;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 1202f42..d766867 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -531,7 +531,7 @@  static bool intel_fbdev_init_bios(struct drm_device *dev,
 	struct intel_framebuffer *fb = NULL;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
-	struct intel_plane_config *plane_config = NULL;
+	struct intel_initial_plane_config *plane_config = NULL;
 	unsigned int max_size = 0;
 
 	if (!i915.fastboot)