diff mbox

drm/i915/bdw: Implement WaForceContextSaveRestoreNonCoherent

Message ID 1422382393-27482-1-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien Jan. 27, 2015, 6:13 p.m. UTC
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
 2 files changed, 3 insertions(+)

Comments

Jani Nikula Jan. 28, 2015, 9:21 a.m. UTC | #1
On Tue, 27 Jan 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:

Missing commit message. I need some description to decide whether this
is required for fixes/stable or not.

BR,
Jani.


> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ae8ea42..47bc4e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5253,6 +5253,7 @@ enum punit_power_well {
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				0x7300
> +#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
>  #define  HDC_FORCE_NON_COHERENT			(1<<4)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 36dad33..d393026 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -790,9 +790,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	 */
>  	/* WaForceEnableNonCoherent:bdw */
>  	/* WaHdcDisableFetchWhenMasked:bdw */
> +	/* WaForceContextSaveRestoreNonCoherent:bdw */
>  	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT |
> +			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
>  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>  			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>  
> -- 
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Lespiau, Damien Jan. 29, 2015, 11:03 a.m. UTC | #2
On Wed, Jan 28, 2015 at 11:21:17AM +0200, Jani Nikula wrote:
> On Tue, 27 Jan 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> 
> Missing commit message. I need some description to decide whether this
> is required for fixes/stable or not.

This patch wasn't prompted by an actual problem I witnessed, but from
going through the list of W/As for SKL.

The need for that W/A was itself discovered through a preemption test,
there's no indication if it could occur with the non-preempted context
switch we do today.

I'd leave it out of fixes/stable then.
Shuang He Jan. 29, 2015, 4:06 p.m. UTC | #3
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5657
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  353/353              353/353
ILK                                  353/353              353/353
SNB                                  400/422              400/422
IVB              +2                 485/487              487/487
BYT                                  296/296              296/296
HSW              +1                 507/508              508/508
BDW                                  401/402              401/402
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 IVB  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(4, M34M21)PASS(5, M4)      PASS(1, M4)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(4, M34M4)PASS(8, M34M4M21)      PASS(1, M4)
 HSW  igt_gem_pwrite_pread_snooped-pwrite-blt-cpu_mmap-performance      DMESG_WARN(1, M40)PASS(13, M40M20)      PASS(1, M40)
Note: You need to pay more attention to line start with '*'
Ville Syrjälä Feb. 2, 2015, 1:44 p.m. UTC | #4
On Tue, Jan 27, 2015 at 06:13:13PM +0000, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

OK, so this has the right w/a name whereas Ben's earlier patch didn't.
So we should go with this version instead.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ae8ea42..47bc4e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5253,6 +5253,7 @@ enum punit_power_well {
>  
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				0x7300
> +#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
>  #define  HDC_FORCE_NON_COHERENT			(1<<4)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>  #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 36dad33..d393026 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -790,9 +790,11 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>  	 */
>  	/* WaForceEnableNonCoherent:bdw */
>  	/* WaHdcDisableFetchWhenMasked:bdw */
> +	/* WaForceContextSaveRestoreNonCoherent:bdw */
>  	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT |
> +			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
>  			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
>  			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>  
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ae8ea42..47bc4e2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5253,6 +5253,7 @@  enum punit_power_well {
 
 /* GEN8 chicken */
 #define HDC_CHICKEN0				0x7300
+#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT	(1<<5)
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 36dad33..d393026 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -790,9 +790,11 @@  static int bdw_init_workarounds(struct intel_engine_cs *ring)
 	 */
 	/* WaForceEnableNonCoherent:bdw */
 	/* WaHdcDisableFetchWhenMasked:bdw */
+	/* WaForceContextSaveRestoreNonCoherent:bdw */
 	/* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 	WA_SET_BIT_MASKED(HDC_CHICKEN0,
 			  HDC_FORCE_NON_COHERENT |
+			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 			  HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));