diff mbox

[1/2] drm/i915: Detect eDRAM with the enabled bit only

Message ID 1422973515-8697-1-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien Feb. 3, 2015, 2:25 p.m. UTC
At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
eDRAM capabilities).

To be more future proof, only look at bit 0 to detect eDRAM presence.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 drivers/gpu/drm/i915/intel_uncore.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

Comments

Paulo Zanoni Feb. 11, 2015, 3:27 p.m. UTC | #1
2015-02-03 12:25 GMT-02:00 Damien Lespiau <damien.lespiau@intel.com>:
> At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
> to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
> eDRAM capabilities).
>
> To be more future proof, only look at bit 0 to detect eDRAM presence.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

For both patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h     | 1 +
>  drivers/gpu/drm/i915/intel_uncore.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33b3d0a2..0aeaf7d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5980,6 +5980,7 @@ enum punit_power_well {
>  #define  HSW_IDICR                             0x9008
>  #define    IDIHASHMSK(x)                       (((x) & 0x3f) << 16)
>  #define  HSW_EDRAM_PRESENT                     0x120010
> +#define    EDRAM_ENABLED                       0x1
>
>  #define GEN6_UCGCTL1                           0x9400
>  # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE             (1 << 16)
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 76b60a3..00c91be 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -328,7 +328,7 @@ static void intel_uncore_ellc_detect(struct drm_device *dev)
>         struct drm_i915_private *dev_priv = dev->dev_private;
>
>         if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
> -           (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
> +           (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
>                 /* The docs do not explain exactly how the calculation can be
>                  * made. It is somewhat guessable, but for now, it's always
>                  * 128MB.
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter Feb. 11, 2015, 3:47 p.m. UTC | #2
On Wed, Feb 11, 2015 at 01:27:14PM -0200, Paulo Zanoni wrote:
> 2015-02-03 12:25 GMT-02:00 Damien Lespiau <damien.lespiau@intel.com>:
> > At the moment we compare the whole EDRAM_PRESENT/EDRAMCAP register value
> > to 1 while EDRAM_PRESENT is only bit 0 (the rest may be used to describe
> > eDRAM capabilities).
> >
> > To be more future proof, only look at bit 0 to detect eDRAM presence.
> >
> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
> 
> For both patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Both merged, thanks for patches&review.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33b3d0a2..0aeaf7d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5980,6 +5980,7 @@  enum punit_power_well {
 #define  HSW_IDICR				0x9008
 #define    IDIHASHMSK(x)			(((x) & 0x3f) << 16)
 #define  HSW_EDRAM_PRESENT			0x120010
+#define    EDRAM_ENABLED			0x1
 
 #define GEN6_UCGCTL1				0x9400
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE		(1 << 16)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 76b60a3..00c91be 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -328,7 +328,7 @@  static void intel_uncore_ellc_detect(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
-	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
+	    (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
 		/* The docs do not explain exactly how the calculation can be
 		 * made. It is somewhat guessable, but for now, it's always
 		 * 128MB.