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[2/7] drm/i915/skl: Updated the gen6_set_rps function

Message ID 1423234598-14781-3-git-send-email-akash.goel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

akash.goel@intel.com Feb. 6, 2015, 2:56 p.m. UTC 
From: Akash Goel <akash.goel@intel.com>

On SKL, the frequency programmed in RPNSWREQ (A008) register
has to be in units of 16.66 MHZ. So updated the gen6_set_rps
function, as per this change.

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

Lespiau, Damien Feb. 17, 2015, 2:31 p.m. UTC | #1 
On Fri, Feb 06, 2015 at 08:26:33PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> On SKL, the frequency programmed in RPNSWREQ (A008) register
> has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> function, as per this change.
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---

Right, we suppose here that val in in 16.66 Mhz units. At the very least
we need update the trace point:

  trace_intel_gpu_freq_change(val * 50);

Then val is passed to gen6_rps_limits(). The values of 0xA014 are also
in 16.66 Mhz units, so that part is fine, but the fields of that
register have changed a bit so we also need to update gen6_rps_limits()
for gen9 (if not done by a later patch).
Lespiau, Damien Feb. 17, 2015, 3:08 p.m. UTC | #2 
On Tue, Feb 17, 2015 at 02:31:08PM +0000, Damien Lespiau wrote:
> On Fri, Feb 06, 2015 at 08:26:33PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > On SKL, the frequency programmed in RPNSWREQ (A008) register
> > has to be in units of 16.66 MHZ. So updated the gen6_set_rps
> > function, as per this change.
> > 
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> 
> Right, we suppose here that val in in 16.66 Mhz units. At the very least
> we need update the trace point:
> 
>   trace_intel_gpu_freq_change(val * 50);
> 
> Then val is passed to gen6_rps_limits(). The values of 0xA014 are also
> in 16.66 Mhz units, so that part is fine, but the fields of that
> register have changed a bit so we also need to update gen6_rps_limits()
> for gen9 (if not done by a later patch).

I managed to get quite confused, I blame the lack of sleep. From
RP_STATE_CAP, we get all the limits in 50Mhz and we store them like
this. So everything is done in units of 50Mhz and then converted to
units of 16.66Mhz at write time. Took me the whole series to realize
that, sorry.

So:

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..58c8c0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3764,7 +3764,10 @@  static void gen6_set_rps(struct drm_device *dev, u8 val)
 	if (val != dev_priv->rps.cur_freq) {
 		gen6_set_rps_thresholds(dev_priv, val);
 
-		if (IS_HASWELL(dev) || IS_BROADWELL(dev))
+		if (IS_GEN9(dev))
+                        I915_WRITE(GEN6_RPNSWREQ,
+                                   GEN9_FREQUENCY(val * GEN9_FREQ_SCALER));
+		else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 			I915_WRITE(GEN6_RPNSWREQ,
 				   HSW_FREQUENCY(val));
 		else