drm/i915/skl: Add check for minimum allocable Display Data Blocks

Commit Message

Kumar, Mahesh Feb. 9, 2015, 9:36 a.m. UTC

Fifo Underrun is observed when allocating < minimum allocable blocks
for any plane, This patch calculate & checks for upper & lower DDB
bound for each plane according to total allocated DDB for that Pipe.

Signed-off-by: Kumar, Mahesh <[e-mail]>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 48 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 50 insertions(+)

Comments

Lespiau, Damien Feb. 9, 2015, 1:28 p.m. UTC | #1

On Mon, Feb 09, 2015 at 03:06:09PM +0530, Kumar, Mahesh wrote:
> Fifo Underrun is observed when allocating < minimum allocable blocks
> for any plane, This patch calculate & checks for upper & lower DDB
> bound for each plane according to total allocated DDB for that Pipe.
> 
> Signed-off-by: Kumar, Mahesh <[e-mail]>

Hi,

It seems that my fix for that got lost (sigh):

  http://lists.freedesktop.org/archives/intel-gfx/2014-October/053713.html

Would you mind reviewing that one instead?

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26ffe8b..fe51a5a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1536,6 +1536,8 @@  struct skl_ddb_allocation {
 	struct skl_ddb_entry pipe[I915_MAX_PIPES];
 	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
 	struct skl_ddb_entry cursor[I915_MAX_PIPES];
+	uint16_t min_alloc[I915_MAX_PIPES][I915_MAX_PLANES];
+	uint16_t max_alloc[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_wm_values {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3c64810..d4d8994 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2482,6 +2482,43 @@  skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
 }
 
 static void
+skl_calculate_allocable_blocks(struct intel_crtc *intel_crtc,
+			const struct skl_pipe_wm_parameters *params,
+			uint16_t alloc_size, struct skl_ddb_allocation *ddb)
+{
+	uint16_t min;
+	uint16_t total_min_alloc = 0;
+	enum pipe pipe = intel_crtc->pipe;
+	int plane;
+
+	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
+		const struct intel_plane_wm_parameters *p;
+
+		p = &params->plane[plane];
+		ddb->min_alloc[pipe][plane] = 0;
+
+		if (!p->enabled)
+			continue;
+
+		/*
+		 * TODO: Calculate PlaneMinAlloc according to X/Y-Tiling
+		 * calculation, for now use X-Tiling PlaneMinAlloc
+		 */
+
+		min = 8;
+
+		ddb->min_alloc[pipe][plane] = min;
+		total_min_alloc += min;
+
+	}
+
+	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
+		ddb->max_alloc[pipe][plane] = alloc_size - total_min_alloc +
+			ddb->min_alloc[pipe][plane];
+	}
+}
+
+static void
 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 		      const struct intel_wm_config *config,
 		      const struct skl_pipe_wm_parameters *params,
@@ -2519,6 +2556,8 @@  skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 	total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
 
 	start = alloc->start;
+
+	skl_calculate_allocable_blocks(intel_crtc, params, alloc_size, ddb);
 	for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
 		const struct intel_plane_wm_parameters *p;
 		unsigned int data_rate;
@@ -2537,6 +2576,15 @@  skl_allocate_pipe_ddb(struct drm_crtc *crtc,
 		plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
 				       total_data_rate);
 
+		/*
+		 * Limit plane_blocks if out of limit
+		 */
+
+		if (plane_blocks > ddb->max_alloc[pipe][plane])
+			plane_blocks = ddb->max_alloc[pipe][plane];
+		if (plane_blocks < ddb->min_alloc[pipe][plane])
+			plane_blocks = ddb->min_alloc[pipe][plane];
+
 		ddb->plane[pipe][plane].start = start;
 		ddb->plane[pipe][plane].end = start + plane_blocks;