| Message ID | 1423510402-12605-15-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/02/2015 19:33, Damien Lespiau wrote: > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 5 +++++ > 3 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index c0b8644..0765bd1 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2391,6 +2391,7 @@ struct drm_i915_cmd_table { > #define SKL_REVID_B0 (0x1) > #define SKL_REVID_C0 (0x2) > #define SKL_REVID_D0 (0x3) > +#define SKL_REVID_E0 (0x4) > > /* > * The genX designation typically refers to the render engine, so render > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d519ed9..3ae7a09 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5264,6 +5264,9 @@ enum skl_disp_power_wells { > #define GEN7_L3SQCREG4 0xb034 > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > +#define GEN8_L3SQCREG4 0xb118 > +#define GEN8_LQSC_RO_PERF_DIS (1<<27) > + > /* GEN8 chicken */ > #define HDC_CHICKEN0 0x7300 > #define HDC_FORCE_NON_COHERENT (1<<4) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ff4e289..f53ef11 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -80,6 +80,11 @@ static void skl_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | > GEN6_VFUNIT_CLOCK_GATE_DISABLE); > } > + > + if (INTEL_REVID(dev) <= SKL_REVID_E0) > + /* WaDisableLSQCROPERFforOCL:skl */ > + I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | > + GEN8_LQSC_RO_PERF_DIS); > } > > static void i915_pineview_get_mem_freq(struct drm_device *dev) >
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c0b8644..0765bd1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2391,6 +2391,7 @@ struct drm_i915_cmd_table { #define SKL_REVID_B0 (0x1) #define SKL_REVID_C0 (0x2) #define SKL_REVID_D0 (0x3) +#define SKL_REVID_E0 (0x4) /* * The genX designation typically refers to the render engine, so render diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d519ed9..3ae7a09 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5264,6 +5264,9 @@ enum skl_disp_power_wells { #define GEN7_L3SQCREG4 0xb034 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) +#define GEN8_L3SQCREG4 0xb118 +#define GEN8_LQSC_RO_PERF_DIS (1<<27) + /* GEN8 chicken */ #define HDC_CHICKEN0 0x7300 #define HDC_FORCE_NON_COHERENT (1<<4) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ff4e289..f53ef11 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -80,6 +80,11 @@ static void skl_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | GEN6_VFUNIT_CLOCK_GATE_DISABLE); } + + if (INTEL_REVID(dev) <= SKL_REVID_E0) + /* WaDisableLSQCROPERFforOCL:skl */ + I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | + GEN8_LQSC_RO_PERF_DIS); } static void i915_pineview_get_mem_freq(struct drm_device *dev)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 5 +++++ 3 files changed, 9 insertions(+)