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[18/18] drm/i915/skl: Implement WaBarrierPerformanceFixDisable

Message ID 1423510402-12605-19-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien Feb. 9, 2015, 7:33 p.m. UTC 
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
 2 files changed, 8 insertions(+)

Comments

Shuang He Feb. 10, 2015, 2:02 p.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5737
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/283              282/283
ILK                                  308/315              308/315
SNB              +1-22              340/346              319/346
IVB              +1-2              378/384              377/384
BYT                                  296/296              296/296
HSW              +2                 421/428              423/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*SNB  igt_kms_flip_dpms-vs-vblank-race      PASS(4, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(3, M22)PASS(2, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_pipe_crc_basic_read-crc-pipe-A      DMESG_WARN(1, M22)PASS(6, M22)      PASS(1, M22)
 SNB  igt_kms_rotation_crc_primary-rotation      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_kms_rotation_crc_sprite-rotation      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_cursor-dpms      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-mode-unset-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_dpms-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_drm-resources-equal      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_fences-dpms      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-execbuf      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-cpu      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-mmap-gtt      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_gem-pread      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_i2c      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_modeset-non-lpsp-stress-no-wait      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_pci-d3-state      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 SNB  igt_pm_rpm_rte      NSPT(2, M22)PASS(1, M22)      NSPT(1, M22)
 IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1, M34)PASS(5, M34)      DMESG_WARN(1, M34)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(2, M34)PASS(2, M34)      PASS(1, M34)
 IVB  igt_gem_storedw_batches_loop_secure-dispatch      DMESG_WARN(1, M34)PASS(3, M34)      DMESG_WARN(1, M34)
 HSW  igt_gem_storedw_loop_blt      DMESG_WARN(3, M20)PASS(3, M20)      PASS(1, M20)
 HSW  igt_gem_storedw_loop_vebox      DMESG_WARN(3, M20)PASS(2, M20)      PASS(1, M20)
Note: You need to pay more attention to line start with '*'
Nick Hoath Feb. 11, 2015, 3:51 p.m. UTC | #2 
On 09/02/2015 19:33, Damien Lespiau wrote:
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>

> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++++++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 090ddd7..b4abd50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5276,6 +5276,7 @@ enum skl_disp_power_wells {
>   #define  HDC_FORCE_NON_COHERENT			(1<<4)
>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
>   #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
> +#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
>
>   /* WaCatErrorRejectionIssue */
>   #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 57432ca..93365fe 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -947,6 +947,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>   		WA_SET_BIT_MASKED(HIZ_CHICKEN,
>   				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
>
> +	if (INTEL_REVID(dev) == SKL_REVID_C0 ||
> +	    INTEL_REVID(dev) == SKL_REVID_D0)
> +		/* WaBarrierPerformanceFixDisable:skl */
> +		WA_SET_BIT_MASKED(HDC_CHICKEN0,
> +				  HDC_FENCE_DEST_SLM_DISABLE |
> +				  HDC_BARRIER_PERFORMANCE_DISABLE);
> +
>   	return 0;
>   }
>
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 090ddd7..b4abd50 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5276,6 +5276,7 @@  enum skl_disp_power_wells {
 #define  HDC_FORCE_NON_COHERENT			(1<<4)
 #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED	(1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE		(1<<14)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 57432ca..93365fe 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -947,6 +947,13 @@  static int skl_init_workarounds(struct intel_engine_cs *ring)
 		WA_SET_BIT_MASKED(HIZ_CHICKEN,
 				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
 
+	if (INTEL_REVID(dev) == SKL_REVID_C0 ||
+	    INTEL_REVID(dev) == SKL_REVID_D0)
+		/* WaBarrierPerformanceFixDisable:skl */
+		WA_SET_BIT_MASKED(HDC_CHICKEN0,
+				  HDC_FENCE_DEST_SLM_DISABLE |
+				  HDC_BARRIER_PERFORMANCE_DISABLE);
+
 	return 0;
 }