Message ID | 1423574909-1074-9-git-send-email-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Poke at the CBR1_VLV register during init_clock_gating to make sure the > PND deadline scheme is used. > > The hardware has two modes of operation wrt. watermarks: > > 1) PND deadline mode: > - memory request deadline is calculated from actual FIFO level * DDL > - WM1 watermark values are unused (AFAIK) > - WM watermark level defines when to start fetching data from memory > (assuming trickle feed is not used) > > 2) backup mode > - deadline is based on FIFO status, DDL is unused > - FIFO split into three regions with WM and WM1 watermarks, each > part specifying a different FIFO status > > We want to use the PND deadline mode, so let's make sure the chicken > bit is in the correct position on init. > > Also take the opportunity to refactor the shared code between VLV and > CHV to a shared function. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------ > 2 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 433d7e7..5d377df 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells { > #define DDL_PRECISION_LOW (0<<7) > #define DRAIN_LATENCY_MASK 0x7f > > +#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400) > +#define CBR_PND_DEADLINE_DISABLE (1<<31) > + > /* FIFO watermark sizes etc */ > #define G4X_FIFO_LINE_SIZE 64 > #define I915_FIFO_LINE_SIZE 64 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index e53038e..c021e92 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > gen6_check_mch_setup(dev); > } > > +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > + > + /* > + * Disable trickle feed and enable pnd deadline calculation > + */ > + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > + I915_WRITE(CBR1_VLV, 0); > +} > + > static void valleyview_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > + vlv_init_display_clock_gating(dev_priv); > > /* WaDisableEarlyCull:vlv */ > I915_WRITE(_3D_CHICKEN3, > @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN7_UCGCTL4, > I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > - > /* > * BSpec says this must be set, even though > * WaDisable4x2SubspanOptimization isn't listed for VLV. > @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > - > - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > + vlv_init_display_clock_gating(dev_priv); > > /* WaVSRefCountFullforceMissDisable:chv */ > /* WaDSRefCountFullforceMissDisable:chv */ > Is the deadline mode preference documented somewhere? Do we need another bspec bug filed? Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
On Fri, Feb 27, 2015 at 12:38:44PM -0800, Jesse Barnes wrote: > On 02/10/2015 05:28 AM, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Poke at the CBR1_VLV register during init_clock_gating to make sure the > > PND deadline scheme is used. > > > > The hardware has two modes of operation wrt. watermarks: > > > > 1) PND deadline mode: > > - memory request deadline is calculated from actual FIFO level * DDL > > - WM1 watermark values are unused (AFAIK) > > - WM watermark level defines when to start fetching data from memory > > (assuming trickle feed is not used) > > > > 2) backup mode > > - deadline is based on FIFO status, DDL is unused > > - FIFO split into three regions with WM and WM1 watermarks, each > > part specifying a different FIFO status > > > > We want to use the PND deadline mode, so let's make sure the chicken > > bit is in the correct position on init. > > > > Also take the opportunity to refactor the shared code between VLV and > > CHV to a shared function. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > > drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------ > > 2 files changed, 16 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 433d7e7..5d377df 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells { > > #define DDL_PRECISION_LOW (0<<7) > > #define DRAIN_LATENCY_MASK 0x7f > > > > +#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400) > > +#define CBR_PND_DEADLINE_DISABLE (1<<31) > > + > > /* FIFO watermark sizes etc */ > > #define G4X_FIFO_LINE_SIZE 64 > > #define I915_FIFO_LINE_SIZE 64 > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > > index e53038e..c021e92 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) > > gen6_check_mch_setup(dev); > > } > > > > +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) > > +{ > > + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > + > > + /* > > + * Disable trickle feed and enable pnd deadline calculation > > + */ > > + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > + I915_WRITE(CBR1_VLV, 0); > > +} > > + > > static void valleyview_init_clock_gating(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > + vlv_init_display_clock_gating(dev_priv); > > > > /* WaDisableEarlyCull:vlv */ > > I915_WRITE(_3D_CHICKEN3, > > @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > > I915_WRITE(GEN7_UCGCTL4, > > I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > > > > - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > - > > /* > > * BSpec says this must be set, even though > > * WaDisable4x2SubspanOptimization isn't listed for VLV. > > @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev) > > { > > struct drm_i915_private *dev_priv = dev->dev_private; > > > > - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); > > - > > - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); > > + vlv_init_display_clock_gating(dev_priv); > > > > /* WaVSRefCountFullforceMissDisable:chv */ > > /* WaDSRefCountFullforceMissDisable:chv */ > > > > Is the deadline mode preference documented somewhere? Do we need > another bspec bug filed? VLV display cluster HAS had a fairly good description. We can at least hope it works well enough on VLV. Sadly it doesn't actually work the way you'd expect on CHV, but that's a whole other story. > > Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 433d7e7..5d377df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4177,6 +4177,9 @@ enum skl_disp_power_wells { #define DDL_PRECISION_LOW (0<<7) #define DRAIN_LATENCY_MASK 0x7f +#define CBR1_VLV (VLV_DISPLAY_BASE + 0x70400) +#define CBR_PND_DEADLINE_DISABLE (1<<31) + /* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 #define I915_FIFO_LINE_SIZE 64 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e53038e..c021e92 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6197,11 +6197,22 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) gen6_check_mch_setup(dev); } +static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) +{ + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); + + /* + * Disable trickle feed and enable pnd deadline calculation + */ + I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); + I915_WRITE(CBR1_VLV, 0); +} + static void valleyview_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); + vlv_init_display_clock_gating(dev_priv); /* WaDisableEarlyCull:vlv */ I915_WRITE(_3D_CHICKEN3, @@ -6249,8 +6260,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_UCGCTL4, I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); - /* * BSpec says this must be set, even though * WaDisable4x2SubspanOptimization isn't listed for VLV. @@ -6287,9 +6296,7 @@ static void cherryview_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); - - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); + vlv_init_display_clock_gating(dev_priv); /* WaVSRefCountFullforceMissDisable:chv */ /* WaDSRefCountFullforceMissDisable:chv */