| Message ID | 1423678904-23698-3-git-send-email-damien.lespiau@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 11/02/2015 18:21, Lespiau, Damien wrote: > I have no idea how that crept in, but we need to do the write from the > ring and this is a masked register. Two fixes in 1! > > Cc: Nick Hoath <nicholas.hoath@intel.com> > Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++------- > 1 file changed, 3 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 8735e56..acc1669 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) > > if (INTEL_REVID(dev) == SKL_REVID_A0 || > INTEL_REVID(dev) == SKL_REVID_B0) { > - /* > - * WaDisableDgMirrorFixInHalfSliceChicken5:skl > - * This is a pre-production w/a. > - */ > - I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, > - I915_READ(GEN9_HALF_SLICE_CHICKEN5) & > - ~GEN9_DG_MIRROR_FIX_ENABLE); > + /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */ > + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, > + GEN9_DG_MIRROR_FIX_ENABLE); > } > > if (INTEL_REVID(dev) >= SKL_REVID_C0) { >
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5763
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 282/282 282/282
ILK 313/313 313/313
SNB 309/323 309/323
IVB 380/380 380/380
BYT 296/296 296/296
HSW 425/425 425/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BDW igt_gem_gtt_hog PASS(8) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
On Thu, Feb 12, 2015 at 01:36:29PM +0000, Nick Hoath wrote: > On 11/02/2015 18:21, Lespiau, Damien wrote: > >I have no idea how that crept in, but we need to do the write from the > >ring and this is a masked register. Two fixes in 1! > > > >Cc: Nick Hoath <nicholas.hoath@intel.com> > >Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> > > Reviewed-by: Nick Hoath <nicholas.hoath@intel.com> Merged four more skl wa patches, thanks. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8735e56..acc1669 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -959,13 +959,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) if (INTEL_REVID(dev) == SKL_REVID_A0 || INTEL_REVID(dev) == SKL_REVID_B0) { - /* - * WaDisableDgMirrorFixInHalfSliceChicken5:skl - * This is a pre-production w/a. - */ - I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, - I915_READ(GEN9_HALF_SLICE_CHICKEN5) & - ~GEN9_DG_MIRROR_FIX_ENABLE); + /* WaDisableDgMirrorFixInHalfSliceChicken5:skl */ + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, + GEN9_DG_MIRROR_FIX_ENABLE); } if (INTEL_REVID(dev) >= SKL_REVID_C0) {
I have no idea how that crept in, but we need to do the write from the ring and this is a masked register. Two fixes in 1! Cc: Nick Hoath <nicholas.hoath@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-)