diff mbox

[v2,3/5] drm/i915/skl: Restructured the gen6_set_rps_thresholds function

Message ID 1424268078-14541-5-git-send-email-akash.goel@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

akash.goel@intel.com Feb. 18, 2015, 2:01 p.m. UTC 
From: Akash Goel <akash.goel@intel.com>

Prior to SKL, the time period programmed in Up/Down EI & Up/Down
threshold registers was in units of 1.28 micro seconds. But for
SKL, the units have changed (1.333 micro seconds).
Have generalized the implementation of gen6_set_rps_thresholds function,
by removing the hard coding done in it as per 1.28 micro seconds.

v2: Renamed the local variables & removed superfluous comments (Chris)

Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
 1 file changed, 32 insertions(+), 36 deletions(-)

Comments

Lespiau, Damien Feb. 18, 2015, 5:58 p.m. UTC | #1 
On Wed, Feb 18, 2015 at 07:31:15PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Prior to SKL, the time period programmed in Up/Down EI & Up/Down
> threshold registers was in units of 1.28 micro seconds. But for
> SKL, the units have changed (1.333 micro seconds).
> Have generalized the implementation of gen6_set_rps_thresholds function,
> by removing the hard coding done in it as per 1.28 micro seconds.
> 
> v2: Renamed the local variables & removed superfluous comments (Chris)
> 
> Signed-off-by: Akash Goel <akash.goel@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 68 +++++++++++++++++++----------------------
>  1 file changed, 32 insertions(+), 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1df3fbd..78b4d62 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3643,6 +3643,8 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
>  static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  {
>  	int new_power;
> +	u32 threshold_up = 0, threshold_down = 0; /* in % */
> +	u32 ei_up = 0, ei_down = 0;
>  
>  	new_power = dev_priv->rps.power;
>  	switch (dev_priv->rps.power) {
> @@ -3675,59 +3677,53 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
>  	switch (new_power) {
>  	case LOW_POWER:
>  		/* Upclock if more than 95% busy over 16ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 12500);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
> +		ei_up = 16000;
> +		threshold_up = 95;
>  
>  		/* Downclock if less than 85% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 85;
>  		break;
>  
>  	case BETWEEN:
>  		/* Upclock if more than 90% busy over 13ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 10250);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
> +		ei_up = 13000;
> +		threshold_up = 90;
>  
>  		/* Downclock if less than 75% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 75;
>  		break;
>  
>  	case HIGH_POWER:
>  		/* Upclock if more than 85% busy over 10ms */
> -		I915_WRITE(GEN6_RP_UP_EI, 8000);
> -		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
> +		ei_up = 10000;
> +		threshold_up = 85;
>  
>  		/* Downclock if less than 60% busy over 32ms */
> -		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
> -		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
> -
> -		I915_WRITE(GEN6_RP_CONTROL,
> -			   GEN6_RP_MEDIA_TURBO |
> -			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
> -			   GEN6_RP_MEDIA_IS_GFX |
> -			   GEN6_RP_ENABLE |
> -			   GEN6_RP_UP_BUSY_AVG |
> -			   GEN6_RP_DOWN_IDLE_AVG);
> +		ei_down = 32000;
> +		threshold_down = 60;
>  		break;
>  	}
>  
> +	I915_WRITE(GEN6_RP_UP_EI,
> +		GT_INTERVAL_FROM_US(ei_up));
> +	I915_WRITE(GEN6_RP_UP_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
> +
> +	I915_WRITE(GEN6_RP_DOWN_EI,
> +		GT_INTERVAL_FROM_US(ei_down));
> +	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
> +		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
> +
> +	 I915_WRITE(GEN6_RP_CONTROL,
> +		    GEN6_RP_MEDIA_TURBO |
> +		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
> +		    GEN6_RP_MEDIA_IS_GFX |
> +		    GEN6_RP_ENABLE |
> +		    GEN6_RP_UP_BUSY_AVG |
> +		    GEN6_RP_DOWN_IDLE_AVG);
> +
>  	dev_priv->rps.power = new_power;
>  	dev_priv->rps.last_adj = 0;
>  }
> -- 
> 1.9.2
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1df3fbd..78b4d62 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3643,6 +3643,8 @@  static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 {
 	int new_power;
+	u32 threshold_up = 0, threshold_down = 0; /* in % */
+	u32 ei_up = 0, ei_down = 0;
 
 	new_power = dev_priv->rps.power;
 	switch (dev_priv->rps.power) {
@@ -3675,59 +3677,53 @@  static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
 	switch (new_power) {
 	case LOW_POWER:
 		/* Upclock if more than 95% busy over 16ms */
-		I915_WRITE(GEN6_RP_UP_EI, 12500);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
+		ei_up = 16000;
+		threshold_up = 95;
 
 		/* Downclock if less than 85% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 85;
 		break;
 
 	case BETWEEN:
 		/* Upclock if more than 90% busy over 13ms */
-		I915_WRITE(GEN6_RP_UP_EI, 10250);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
+		ei_up = 13000;
+		threshold_up = 90;
 
 		/* Downclock if less than 75% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 75;
 		break;
 
 	case HIGH_POWER:
 		/* Upclock if more than 85% busy over 10ms */
-		I915_WRITE(GEN6_RP_UP_EI, 8000);
-		I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
+		ei_up = 10000;
+		threshold_up = 85;
 
 		/* Downclock if less than 60% busy over 32ms */
-		I915_WRITE(GEN6_RP_DOWN_EI, 25000);
-		I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
-
-		I915_WRITE(GEN6_RP_CONTROL,
-			   GEN6_RP_MEDIA_TURBO |
-			   GEN6_RP_MEDIA_HW_NORMAL_MODE |
-			   GEN6_RP_MEDIA_IS_GFX |
-			   GEN6_RP_ENABLE |
-			   GEN6_RP_UP_BUSY_AVG |
-			   GEN6_RP_DOWN_IDLE_AVG);
+		ei_down = 32000;
+		threshold_down = 60;
 		break;
 	}
 
+	I915_WRITE(GEN6_RP_UP_EI,
+		GT_INTERVAL_FROM_US(ei_up));
+	I915_WRITE(GEN6_RP_UP_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_up * threshold_up / 100)));
+
+	I915_WRITE(GEN6_RP_DOWN_EI,
+		GT_INTERVAL_FROM_US(ei_down));
+	I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
+		GT_INTERVAL_FROM_US((ei_down * threshold_down / 100)));
+
+	 I915_WRITE(GEN6_RP_CONTROL,
+		    GEN6_RP_MEDIA_TURBO |
+		    GEN6_RP_MEDIA_HW_NORMAL_MODE |
+		    GEN6_RP_MEDIA_IS_GFX |
+		    GEN6_RP_ENABLE |
+		    GEN6_RP_UP_BUSY_AVG |
+		    GEN6_RP_DOWN_IDLE_AVG);
+
 	dev_priv->rps.power = new_power;
 	dev_priv->rps.last_adj = 0;
 }