| Message ID | 1424272568-5920-4-git-send-email-nicholas.hoath@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Feb 18, 2015 at 03:16:08PM +0000, Nick Hoath wrote:
> Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Can you please prefix subjects by drm/i915/skl or drm/i915/gen9? that
helps people doing selective backports. In any case, we at least use
drm/i915 as prefixes, not empty like here :).
While you're enabling the write to SP here, are the second part of the
W/A (setting it to 0) done in the shader? As always the
documentation/bug report are very thin...
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5791
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 277/277 276/277
ILK 313/313 313/313
SNB 309/309 309/309
IVB -1 382/382 381/382
BYT 296/296 296/296
HSW 425/425 425/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync NO_RESULT(1)CRASH(3)PASS(3) CRASH(2)
*IVB igt_gem_storedw_batches_loop_normal PASS(4) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(9) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
On Wed, Feb 18, 2015 at 06:48:11PM +0000, Damien Lespiau wrote: > On Wed, Feb 18, 2015 at 03:16:08PM +0000, Nick Hoath wrote: > > Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> > > Can you please prefix subjects by drm/i915/skl or drm/i915/gen9? that > helps people doing selective backports. In any case, we at least use > drm/i915 as prefixes, not empty like here :). > > While you're enabling the write to SP here, are the second part of the > W/A (setting it to 0) done in the shader? As always the > documentation/bug report are very thin... If there's a part to be done in shaders we need to audit rendercpy, mesa, libva, ddx and everything else too ... Please cc relevant lists/maintainers for the next iteration. Thanks, Daniel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7f9150b..0326399 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6216,6 +6216,7 @@ enum skl_disp_power_wells { #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) #define GEN8_ROW_CHICKEN 0xe4f0 +#define ENABLE_FLOW_CONTROL_WRITES (1<<15) #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) #define STALL_DOP_GATING_DISABLE (1<<5) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2060610..36df3d4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -950,7 +950,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) struct drm_i915_private *dev_priv = dev->dev_private; /* WaDisablePartialInstShootdown:skl */ + /* WaClearFlowControlGpgpuContextSave:skl */ WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, + ENABLE_FLOW_CONTROL_WRITES | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); /* Syncing dependencies between camera and graphics */
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ 2 files changed, 3 insertions(+)