diff mbox

[37/53] drm/i915: Update ring->flush() to take a requests structure

Message ID 1424366285-29232-38-git-send-email-John.C.Harrison@Intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

John Harrison Feb. 19, 2015, 5:17 p.m. UTC 
From: John Harrison <John.C.Harrison@Intel.com>

Udpated the various ring->flush() functions to take a request instead of a ring.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/i915_gem_context.c |    2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c     |    6 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.c |   30 +++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_ringbuffer.h |    2 +-
 4 files changed, 24 insertions(+), 16 deletions(-)

Comments

Tomas Elf March 9, 2015, 8:40 p.m. UTC | #1 
On 19/02/2015 17:17, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Udpated the various ring->flush() functions to take a request instead of a ring.
>
> For: VIZ-5115
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_context.c |    2 +-
>   drivers/gpu/drm/i915/i915_gem_gtt.c     |    6 +++---
>   drivers/gpu/drm/i915/intel_ringbuffer.c |   30 +++++++++++++++++++-----------
>   drivers/gpu/drm/i915/intel_ringbuffer.h |    2 +-
>   4 files changed, 24 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 816a442..384f481 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -489,7 +489,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>   	 * itlb_before_ctx_switch.
>   	 */
>   	if (IS_GEN6(ring->dev)) {
> -		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
> +		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
>   		if (ret)
>   			return ret;
>   	}
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c3408f2..a1af644 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -784,7 +784,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   	int ret;
>
>   	/* NB: TLBs must be flushed and invalidated before a switch */
> -	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> +	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
>   	if (ret)
>   		return ret;
>
> @@ -821,7 +821,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   	int ret;
>
>   	/* NB: TLBs must be flushed and invalidated before a switch */
> -	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> +	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
>   	if (ret)
>   		return ret;
>
> @@ -839,7 +839,7 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
>
>   	/* XXX: RCS is the only one to auto invalidate the TLBs? */
>   	if (ring->id != RCS) {
> -		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> +		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
>   		if (ret)
>   			return ret;
>   	}
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 91a9131..ca8f039 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -91,10 +91,11 @@ static void __intel_ring_advance(struct intel_engine_cs *ring)
>   }
>
>   static int
> -gen2_render_ring_flush(struct intel_engine_cs *ring,
> +gen2_render_ring_flush(struct drm_i915_gem_request *req,
>   		       u32	invalidate_domains,
>   		       u32	flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	u32 cmd;
>   	int ret;
>
> @@ -117,10 +118,11 @@ gen2_render_ring_flush(struct intel_engine_cs *ring,
>   }
>
>   static int
> -gen4_render_ring_flush(struct intel_engine_cs *ring,
> +gen4_render_ring_flush(struct drm_i915_gem_request *req,
>   		       u32	invalidate_domains,
>   		       u32	flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	struct drm_device *dev = ring->dev;
>   	u32 cmd;
>   	int ret;
> @@ -247,9 +249,10 @@ intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
>   }
>
>   static int
> -gen6_render_ring_flush(struct intel_engine_cs *ring,
> -                         u32 invalidate_domains, u32 flush_domains)
> +gen6_render_ring_flush(struct drm_i915_gem_request *req,
> +		       u32 invalidate_domains, u32 flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	u32 flags = 0;
>   	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
>   	int ret;
> @@ -341,9 +344,10 @@ static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
>   }
>
>   static int
> -gen7_render_ring_flush(struct intel_engine_cs *ring,
> +gen7_render_ring_flush(struct drm_i915_gem_request *req,
>   		       u32 invalidate_domains, u32 flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	u32 flags = 0;
>   	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
>   	int ret;
> @@ -426,9 +430,10 @@ gen8_emit_pipe_control(struct intel_engine_cs *ring,
>   }
>
>   static int
> -gen8_render_ring_flush(struct intel_engine_cs *ring,
> +gen8_render_ring_flush(struct drm_i915_gem_request *req,
>   		       u32 invalidate_domains, u32 flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	u32 flags = 0;
>   	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
>   	int ret;
> @@ -1527,10 +1532,11 @@ i8xx_ring_put_irq(struct intel_engine_cs *ring)
>   }
>
>   static int
> -bsd_ring_flush(struct intel_engine_cs *ring,
> +bsd_ring_flush(struct drm_i915_gem_request *req,
>   	       u32     invalidate_domains,
>   	       u32     flush_domains)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	int ret;
>
>   	ret = intel_ring_begin(ring, 2);
> @@ -2318,9 +2324,10 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
>   		   _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
>   }
>
> -static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
> +static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
>   			       u32 invalidate, u32 flush)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	uint32_t cmd;
>   	int ret;
>
> @@ -2430,9 +2437,10 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
>
>   /* Blitter support (SandyBridge+) */
>
> -static int gen6_ring_flush(struct intel_engine_cs *ring,
> +static int gen6_ring_flush(struct drm_i915_gem_request *req,
>   			   u32 invalidate, u32 flush)
>   {
> +	struct intel_engine_cs *ring = req->ring;
>   	struct drm_device *dev = ring->dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	uint32_t cmd;
> @@ -2854,7 +2862,7 @@ intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
>   	if (!ring->gpu_caches_dirty)
>   		return 0;
>
> -	ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
> +	ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
>   	if (ret)
>   		return ret;
>
> @@ -2875,7 +2883,7 @@ intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
>   	if (ring->gpu_caches_dirty)
>   		flush_domains = I915_GEM_GPU_DOMAINS;
>
> -	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
> +	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
>   	if (ret)
>   		return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 0ef29fb..c08e2dc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -147,7 +147,7 @@ struct  intel_engine_cs {
>
>   	void		(*write_tail)(struct intel_engine_cs *ring,
>   				      u32 value);
> -	int __must_check (*flush)(struct intel_engine_cs *ring,
> +	int __must_check (*flush)(struct drm_i915_gem_request *req,
>   				  u32	invalidate_domains,
>   				  u32	flush_domains);
>   	int		(*add_request)(struct intel_engine_cs *ring);
>

trace_i915_gem_ring_flush still takes a ring as input argument. Do you 
feel like updating it to reflect your changes?

Thanks,
Tomas
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 816a442..384f481 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -489,7 +489,7 @@  mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
 	 * itlb_before_ctx_switch.
 	 */
 	if (IS_GEN6(ring->dev)) {
-		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
+		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
 		if (ret)
 			return ret;
 	}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c3408f2..a1af644 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -784,7 +784,7 @@  static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 	int ret;
 
 	/* NB: TLBs must be flushed and invalidated before a switch */
-	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 
@@ -821,7 +821,7 @@  static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 	int ret;
 
 	/* NB: TLBs must be flushed and invalidated before a switch */
-	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 
@@ -839,7 +839,7 @@  static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 
 	/* XXX: RCS is the only one to auto invalidate the TLBs? */
 	if (ring->id != RCS) {
-		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 		if (ret)
 			return ret;
 	}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 91a9131..ca8f039 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -91,10 +91,11 @@  static void __intel_ring_advance(struct intel_engine_cs *ring)
 }
 
 static int
-gen2_render_ring_flush(struct intel_engine_cs *ring,
+gen2_render_ring_flush(struct drm_i915_gem_request *req,
 		       u32	invalidate_domains,
 		       u32	flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	u32 cmd;
 	int ret;
 
@@ -117,10 +118,11 @@  gen2_render_ring_flush(struct intel_engine_cs *ring,
 }
 
 static int
-gen4_render_ring_flush(struct intel_engine_cs *ring,
+gen4_render_ring_flush(struct drm_i915_gem_request *req,
 		       u32	invalidate_domains,
 		       u32	flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	struct drm_device *dev = ring->dev;
 	u32 cmd;
 	int ret;
@@ -247,9 +249,10 @@  intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 }
 
 static int
-gen6_render_ring_flush(struct intel_engine_cs *ring,
-                         u32 invalidate_domains, u32 flush_domains)
+gen6_render_ring_flush(struct drm_i915_gem_request *req,
+		       u32 invalidate_domains, u32 flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	u32 flags = 0;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 	int ret;
@@ -341,9 +344,10 @@  static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 }
 
 static int
-gen7_render_ring_flush(struct intel_engine_cs *ring,
+gen7_render_ring_flush(struct drm_i915_gem_request *req,
 		       u32 invalidate_domains, u32 flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	u32 flags = 0;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 	int ret;
@@ -426,9 +430,10 @@  gen8_emit_pipe_control(struct intel_engine_cs *ring,
 }
 
 static int
-gen8_render_ring_flush(struct intel_engine_cs *ring,
+gen8_render_ring_flush(struct drm_i915_gem_request *req,
 		       u32 invalidate_domains, u32 flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	u32 flags = 0;
 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 	int ret;
@@ -1527,10 +1532,11 @@  i8xx_ring_put_irq(struct intel_engine_cs *ring)
 }
 
 static int
-bsd_ring_flush(struct intel_engine_cs *ring,
+bsd_ring_flush(struct drm_i915_gem_request *req,
 	       u32     invalidate_domains,
 	       u32     flush_domains)
 {
+	struct intel_engine_cs *ring = req->ring;
 	int ret;
 
 	ret = intel_ring_begin(ring, 2);
@@ -2318,9 +2324,10 @@  static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
 		   _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
 }
 
-static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
+static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
 			       u32 invalidate, u32 flush)
 {
+	struct intel_engine_cs *ring = req->ring;
 	uint32_t cmd;
 	int ret;
 
@@ -2430,9 +2437,10 @@  gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
 /* Blitter support (SandyBridge+) */
 
-static int gen6_ring_flush(struct intel_engine_cs *ring,
+static int gen6_ring_flush(struct drm_i915_gem_request *req,
 			   u32 invalidate, u32 flush)
 {
+	struct intel_engine_cs *ring = req->ring;
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t cmd;
@@ -2854,7 +2862,7 @@  intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
 	if (!ring->gpu_caches_dirty)
 		return 0;
 
-	ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
+	ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 
@@ -2875,7 +2883,7 @@  intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
 	if (ring->gpu_caches_dirty)
 		flush_domains = I915_GEM_GPU_DOMAINS;
 
-	ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
+	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0ef29fb..c08e2dc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -147,7 +147,7 @@  struct  intel_engine_cs {
 
 	void		(*write_tail)(struct intel_engine_cs *ring,
 				      u32 value);
-	int __must_check (*flush)(struct intel_engine_cs *ring,
+	int __must_check (*flush)(struct drm_i915_gem_request *req,
 				  u32	invalidate_domains,
 				  u32	flush_domains);
 	int		(*add_request)(struct intel_engine_cs *ring);