From patchwork Mon Feb 23 15:44:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 5866471 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6BD709F695 for ; Mon, 23 Feb 2015 15:45:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5B6D120645 for ; Mon, 23 Feb 2015 15:45:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D6D9120624 for ; Mon, 23 Feb 2015 15:45:01 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1702A6E45B; Mon, 23 Feb 2015 07:45:01 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 43CB66E450 for ; Mon, 23 Feb 2015 07:44:57 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 23 Feb 2015 07:39:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,631,1418112000"; d="scan'208";a="682051185" Received: from michelth-linux.isw.intel.com ([10.102.226.150]) by fmsmga002.fm.intel.com with ESMTP; 23 Feb 2015 07:44:55 -0800 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Mon, 23 Feb 2015 15:44:26 +0000 Message-Id: <1424706272-3016-27-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1424706272-3016-1-git-send-email-michel.thierry@intel.com> References: <1418922621-25818-1-git-send-email-michel.thierry@intel.com> <1424706272-3016-1-git-send-email-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v5 26/32] drm/i915/bdw: Add 4 level switching infrastructure X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky Map is easy, it's the same register as the PDP descriptor 0, but it only has one entry. v2: PML4 update in legacy context switch is left for historic reasons, the preferred mode of operation is with lrc context based submission. Signed-off-by: Ben Widawsky Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_gtt.c | 56 +++++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_gem_gtt.h | 4 ++- drivers/gpu/drm/i915/i915_reg.h | 1 + 3 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 44f8fa5..2c3f2db 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -192,6 +192,9 @@ static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, return pde; } +#define gen8_pdpe_encode gen8_pde_encode +#define gen8_pml4e_encode gen8_pde_encode + static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, enum i915_cache_level level, bool valid, u32 unused) @@ -591,8 +594,8 @@ static int gen8_write_pdp(struct intel_engine_cs *ring, return 0; } -static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, - struct intel_engine_cs *ring) +static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, + struct intel_engine_cs *ring) { int i, ret; @@ -609,6 +612,12 @@ static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, return 0; } +static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, + struct intel_engine_cs *ring) +{ + return gen8_write_pdp(ring, 0, ppgtt->pml4.daddr); +} + static void gen8_ppgtt_clear_range(struct i915_address_space *vm, uint64_t start, uint64_t length, @@ -752,6 +761,37 @@ static void gen8_map_pagetable_range(struct i915_address_space *vm, kunmap_atomic(page_directory); } +static void gen8_map_page_directory(struct i915_page_directory_pointer_entry *pdp, + struct i915_page_directory_entry *pd, + int index, + struct drm_device *dev) +{ + gen8_ppgtt_pdpe_t *page_directorypo; + gen8_ppgtt_pdpe_t pdpe; + + /* We do not need to clflush because no platform requiring flush + * supports 64b pagetables. */ + if (!USES_FULL_48BIT_PPGTT(dev)) + return; + + page_directorypo = kmap_atomic(pdp->page); + pdpe = gen8_pdpe_encode(dev, pd->daddr, I915_CACHE_LLC); + page_directorypo[index] = pdpe; + kunmap_atomic(page_directorypo); +} + +static void gen8_map_page_directory_pointer(struct i915_pml4 *pml4, + struct i915_page_directory_pointer_entry *pdp, + int index, + struct drm_device *dev) +{ + gen8_ppgtt_pml4e_t *pagemap = kmap_atomic(pml4->page); + gen8_ppgtt_pml4e_t pml4e = gen8_pml4e_encode(dev, pdp->daddr, I915_CACHE_LLC); + BUG_ON(!USES_FULL_48BIT_PPGTT(dev)); + pagemap[index] = pml4e; + kunmap_atomic(pagemap); +} + static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) { int i; @@ -1123,6 +1163,7 @@ static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, set_bit(pdpe, pdp->used_pdpes); gen8_map_pagetable_range(vm, pd, start, length); + gen8_map_page_directory(pdp, pd, pdpe, dev); } free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes); @@ -1191,6 +1232,8 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); if (ret) goto err_out; + + gen8_map_page_directory_pointer(pml4, pdp, pml4e, vm->dev); } bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, @@ -1250,14 +1293,14 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; - ppgtt->switch_mm = gen8_mm_switch; - if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { int ret = pml4_init(ppgtt); if (ret) { unmap_and_free_pt(ppgtt->scratch_pd, ppgtt->base.dev); return ret; } + + ppgtt->switch_mm = gen8_48b_mm_switch; } else { int ret = __pdp_init(&ppgtt->pdp, false); if (ret) { @@ -1265,6 +1308,7 @@ static int gen8_ppgtt_init_common(struct i915_hw_ppgtt *ppgtt, uint64_t size) return ret; } + ppgtt->switch_mm = gen8_legacy_mm_switch; trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, 0, 0, GEN8_PML4E_SHIFT); } @@ -1294,6 +1338,7 @@ static int gen8_aliasing_ppgtt_init(struct i915_hw_ppgtt *ppgtt) return ret; } + /* FIXME: PML4 */ gen8_for_each_pdpe(pd, pdp, start, size, temp, pdpe) gen8_map_pagetable_range(&ppgtt->base, pd,start, size); @@ -1498,8 +1543,9 @@ static void gen8_ppgtt_enable(struct drm_device *dev) int j; for_each_ring(ring, dev_priv, j) { + u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_64B : 0; I915_WRITE(RING_MODE_GEN7(ring), - _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); + _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); } } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index 1477f54..1f4cdb1 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -38,7 +38,9 @@ struct drm_i915_file_private; typedef uint32_t gen6_gtt_pte_t; typedef uint64_t gen8_gtt_pte_t; -typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; +typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; +typedef gen8_ppgtt_pde_t gen8_ppgtt_pdpe_t; +typedef gen8_ppgtt_pdpe_t gen8_ppgtt_pml4e_t; #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1dc91de..305e5b7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1338,6 +1338,7 @@ enum skl_disp_power_wells { #define GFX_REPLAY_MODE (1<<11) #define GFX_PSMI_GRANULARITY (1<<10) #define GFX_PPGTT_ENABLE (1<<9) +#define GEN8_GFX_PPGTT_64B (1<<7) #define VLV_DISPLAY_BASE 0x180000 #define VLV_MIPI_BASE VLV_DISPLAY_BASE