From patchwork Mon Feb 23 15:44:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Thierry X-Patchwork-Id: 5866491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4997F9F169 for ; Mon, 23 Feb 2015 15:45:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 54CFA2064B for ; Mon, 23 Feb 2015 15:45:06 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 59D5F20644 for ; Mon, 23 Feb 2015 15:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE86A6E46A; Mon, 23 Feb 2015 07:45:02 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id C076C6E450 for ; Mon, 23 Feb 2015 07:44:59 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 23 Feb 2015 07:40:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,631,1418112000"; d="scan'208";a="682051203" Received: from michelth-linux.isw.intel.com ([10.102.226.150]) by fmsmga002.fm.intel.com with ESMTP; 23 Feb 2015 07:44:57 -0800 From: Michel Thierry To: intel-gfx@lists.freedesktop.org Date: Mon, 23 Feb 2015 15:44:29 +0000 Message-Id: <1424706272-3016-30-git-send-email-michel.thierry@intel.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1424706272-3016-1-git-send-email-michel.thierry@intel.com> References: <1418922621-25818-1-git-send-email-michel.thierry@intel.com> <1424706272-3016-1-git-send-email-michel.thierry@intel.com> Subject: [Intel-gfx] [PATCH v5 29/32] drm/i915: Plumb sg_iter through va allocation ->maps X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ben Widawsky As a step towards implementing 4 levels, while not discarding the existing pte map functions, we need to pass the sg_iter through. The current function understands to the page directory granularity. An object's pages may span the page directory, and so using the iter directly as we write the PTEs allows the iterator to stay coherent through a VMA mapping operation spanning multiple page table levels. Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c | 46 +++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ad7e274..483dd73 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -691,7 +691,7 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, } static void gen8_ppgtt_insert_pte_entries(struct i915_page_directory_pointer_entry *pdp, - struct sg_table *pages, + struct sg_page_iter *sg_iter, uint64_t start, enum i915_cache_level cache_level, const bool flush) @@ -700,11 +700,10 @@ static void gen8_ppgtt_insert_pte_entries(struct i915_page_directory_pointer_ent unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; - struct sg_page_iter sg_iter; pt_vaddr = NULL; - for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { + while (__sg_page_iter_next(sg_iter)) { if (pt_vaddr == NULL) { struct i915_page_directory_entry *pd = pdp->page_directory[pdpe]; struct i915_page_table_entry *pt = pd->page_tables[pde]; @@ -714,7 +713,7 @@ static void gen8_ppgtt_insert_pte_entries(struct i915_page_directory_pointer_ent } pt_vaddr[pte] = - gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), + gen8_pte_encode(sg_page_iter_dma_address(sg_iter), cache_level, true); if (++pte == GEN8_PTES_PER_PAGE) { if (flush) @@ -743,8 +742,10 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, { struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); struct i915_page_directory_pointer_entry *pdp = &ppgtt->pdp; /* FIXME: 48b */ + struct sg_page_iter sg_iter; - gen8_ppgtt_insert_pte_entries(pdp, pages, start, cache_level, !HAS_LLC(vm->dev)); + __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); + gen8_ppgtt_insert_pte_entries(pdp, &sg_iter, start, cache_level, !HAS_LLC(vm->dev)); } static void __gen8_do_map_pt(gen8_ppgtt_pde_t * const pde, @@ -1106,10 +1107,12 @@ err_out: return -ENOMEM; } -static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, - struct i915_page_directory_pointer_entry *pdp, - uint64_t start, - uint64_t length) +static int __gen8_alloc_vma_range_3lvl(struct i915_address_space *vm, + struct i915_page_directory_pointer_entry *pdp, + struct sg_page_iter *sg_iter, + uint64_t start, + uint64_t length, + u32 flags) { unsigned long *new_page_dirs, **new_page_tables; struct drm_device *dev = vm->dev; @@ -1178,7 +1181,11 @@ static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, gen8_pte_index(pd_start), gen8_pte_count(pd_start, pd_len)); - /* Our pde is now pointing to the pagetable, pt */ + if (sg_iter) { + BUG_ON(!sg_iter->__nents); + gen8_ppgtt_insert_pte_entries(pdp, sg_iter, pd_start, + flags, !HAS_LLC(vm->dev)); + } set_bit(pde, pd->used_pdes); } @@ -1203,10 +1210,12 @@ err_out: return ret; } -static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, - struct i915_pml4 *pml4, - uint64_t start, - uint64_t length) +static int __gen8_alloc_vma_range_4lvl(struct i915_address_space *vm, + struct i915_pml4 *pml4, + struct sg_page_iter *sg_iter, + uint64_t start, + uint64_t length, + u32 flags) { DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); struct i915_hw_ppgtt *ppgtt = @@ -1250,7 +1259,8 @@ static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) { BUG_ON(!pdp); - ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); + ret = __gen8_alloc_vma_range_3lvl(vm, pdp, sg_iter, + start, length, flags); if (ret) goto err_out; @@ -1282,9 +1292,11 @@ static int gen8_alloc_va_range(struct i915_address_space *vm, container_of(vm, struct i915_hw_ppgtt, base); if (USES_FULL_48BIT_PPGTT(vm->dev)) - return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); + return __gen8_alloc_vma_range_4lvl(vm, &ppgtt->pml4, NULL, + start, length, 0); else - return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); + return __gen8_alloc_vma_range_3lvl(vm, &ppgtt->pdp, NULL, + start, length, 0); } static void gen8_ppgtt_fini_common(struct i915_hw_ppgtt *ppgtt)