From patchwork Fri Feb 27 18:22:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: jeff.mcgee@intel.com X-Patchwork-Id: 5902321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BAFDABF440 for ; Fri, 27 Feb 2015 18:01:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DB22E201B9 for ; Fri, 27 Feb 2015 18:01:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 034E22018E for ; Fri, 27 Feb 2015 18:01:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C5396E92F; Fri, 27 Feb 2015 10:01:46 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id B01C06E92E for ; Fri, 27 Feb 2015 10:01:43 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 27 Feb 2015 09:53:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,661,1418112000"; d="scan'208";a="658196254" Received: from jeffdesk.fm.intel.com ([10.19.123.155]) by orsmga001.jf.intel.com with ESMTP; 27 Feb 2015 10:01:43 -0800 From: jeff.mcgee@intel.com To: intel-gfx@lists.freedesktop.org Date: Fri, 27 Feb 2015 10:22:32 -0800 Message-Id: <1425061352-29188-3-git-send-email-jeff.mcgee@intel.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1425061352-29188-1-git-send-email-jeff.mcgee@intel.com> References: <1425061352-29188-1-git-send-email-jeff.mcgee@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915/chv: Add CHV HW status to SSEU status X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jeff McGee Collect the currently enabled counts of slice, subslice, and execution units using the power gate control ack message registers specific to Cherryview. Slice/subslice/EU info and hardware status can now be determined for CHV, so allow the debugfs SSEU status dump to proceed for CHV devices. Signed-off-by: Jeff McGee Reviewed-by: Ville Syrjälä Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_debugfs.c | 31 +++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++ 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 94b3984..e42e79a 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4362,7 +4362,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = dev->dev_private; unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0; - if (INTEL_INFO(dev)->gen < 9) + if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev)) return -ENODEV; seq_puts(m, "SSEU Device Info\n"); @@ -4384,7 +4384,34 @@ static int i915_sseu_status(struct seq_file *m, void *unused) yesno(INTEL_INFO(dev)->has_eu_pg)); seq_puts(m, "SSEU Device Status\n"); - if (IS_SKYLAKE(dev)) { + if (IS_CHERRYVIEW(dev)) { + const int ss_max = 2; + int ss; + u32 sig1[ss_max], sig2[ss_max]; + + sig1[0] = I915_READ(CHV_POWER_SS0_SIG1); + sig1[1] = I915_READ(CHV_POWER_SS1_SIG1); + sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); + sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); + + for (ss = 0; ss < ss_max; ss++) { + unsigned int eu_cnt; + + if (sig1[ss] & CHV_SS_PG_ENABLE) + /* skip disabled subslice */ + continue; + + s_tot = 1; + ss_per++; + eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) + + ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) + + ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + + ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); + eu_tot += eu_cnt; + eu_per = max(eu_per, eu_cnt); + } + ss_tot = ss_per; + } else if (IS_SKYLAKE(dev)) { const int s_max = 3, ss_max = 4; int s, ss; u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a8b205d..659aefc 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6227,6 +6227,17 @@ enum skl_disp_power_wells { #define GEN6_RC6 3 #define GEN6_RC7 4 +#define CHV_POWER_SS0_SIG1 0xa720 +#define CHV_POWER_SS1_SIG1 0xa728 +#define CHV_SS_PG_ENABLE (1<<1) +#define CHV_EU08_PG_ENABLE (1<<9) +#define CHV_EU19_PG_ENABLE (1<<17) +#define CHV_EU210_PG_ENABLE (1<<25) + +#define CHV_POWER_SS0_SIG2 0xa724 +#define CHV_POWER_SS1_SIG2 0xa72c +#define CHV_EU311_PG_ENABLE (1<<1) + #define GEN9_SLICE0_PGCTL_ACK 0x804c #define GEN9_SLICE1_PGCTL_ACK 0x8050 #define GEN9_SLICE2_PGCTL_ACK 0x8054