From patchwork Tue Mar 3 15:03:29 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 5923741 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3D824BF440 for ; Tue, 3 Mar 2015 15:04:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7561020397 for ; Tue, 3 Mar 2015 15:04:11 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6F3C820395 for ; Tue, 3 Mar 2015 15:04:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 04A596E21B; Tue, 3 Mar 2015 07:04:07 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id BAEDB6E21B for ; Tue, 3 Mar 2015 07:04:05 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP; 03 Mar 2015 07:03:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,682,1418112000"; d="scan'208";a="674484553" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.78]) by fmsmga001.fm.intel.com with ESMTP; 03 Mar 2015 07:03:20 -0800 Received: by rosetta (Postfix, from userid 1000) id 8F86380057; Tue, 3 Mar 2015 17:03:30 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Mar 2015 17:03:29 +0200 Message-Id: <1425395009-9899-1-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH] drm/i915: Setup all page directories for gen8 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP If the mappable size is less than what the full range of pdps can address, we end up setting pdps for only the mappable area. The logical context however needs valid pdp entries. Prior to commit 06fda602dbca ("drm/i915: Create page table allocators") we just have been writing pdp entries with dma address of zero instead of valid pdps. This is supposedly bad even if those pdps are not addressed. As commit 06fda602dbca ("drm/i915: Create page table allocators") introduced more dynamic structure for pdps, we ended up oopsing when we populated the lrc context. Analyzing this oops revealed the fact that we have not been writing valid pdps with bsw, as it is doing the ppgtt init with 2gb limit. We should do the right thing and setup the non addressable part pdps/pde/pte to scratch page through the minimal structure by having just pdp with pde entries pointing to same page with pte entries pointing to scratch page. But instead of going through that trouble, setup all the pdps through individual pd pages and pt entries, even for non addressable parts. This way we populate the lrc with valid pdps and gives us a base for dynamic page allocation to introduce code that truncates the page table structure. The regression of oopsing in init was introduced by commit 06fda602dbca ("drm/i915: Create page table allocators") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89350 Tested-by: Valtteri Rantala Cc: Michel Thierry Cc: Ben Widawsky Cc: Ville Syrjälä Signed-off-by: Mika Kuoppala Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index bd95776..848a821 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -709,7 +709,7 @@ static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, */ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) { - const int max_pdp = DIV_ROUND_UP(size, 1 << 30); + const int max_pdp = GEN8_LEGACY_PDPES; const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; int i, j, ret;