From patchwork Thu Mar 5 04:33:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: sonika.jindal@intel.com X-Patchwork-Id: 5943321 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9F9E19F380 for ; Thu, 5 Mar 2015 04:41:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B92CE2037B for ; Thu, 5 Mar 2015 04:41:48 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BE2E82035E for ; Thu, 5 Mar 2015 04:41:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5D9E06E724; Wed, 4 Mar 2015 20:41:47 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 441DB6E724 for ; Wed, 4 Mar 2015 20:41:46 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP; 04 Mar 2015 20:41:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,345,1422950400"; d="scan'208";a="675392975" Received: from sonikaji-desktop.iind.intel.com ([10.223.25.81]) by fmsmga001.fm.intel.com with ESMTP; 04 Mar 2015 20:41:44 -0800 From: Sonika Jindal To: intel-gfx@lists.freedesktop.org Date: Thu, 5 Mar 2015 10:03:58 +0530 Message-Id: <1425530038-9712-1-git-send-email-sonika.jindal@intel.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <20150304100000.GL11371@intel.com> References: <20150304100000.GL11371@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/skl: Read sink supported rates from edp panel X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh). v3: Reading dpcd's supported link rates tables based upon edp version in the same patch. v4: Move version check under is_edp (Satheesh) v5: Using le16 for rates, some naming, and removing nested if block (Ville) v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES (Ville) v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it v8: Checking return value of intel_dp_dpcd_read_wake() (Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Sonika Jindal Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) --- drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 1 + 2 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d1141d3..0ae8454 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1117,6 +1117,33 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) } } +static int +intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates) +{ + struct drm_device *dev = intel_dp_to_dev(intel_dp); + int i = 0; + uint16_t val; + + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) { + /* + * Receiver supports only main-link rate selection by + * link rate table method, so read link rates from + * supported_link_rates + */ + for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) { + val = le16_to_cpu(intel_dp->supported_rates[i]); + if (val == 0) + break; + + sink_rates[i] = val * 200; + } + + if (i <= 0) + DRM_ERROR("No rates in SUPPORTED_LINK_RATES"); + } + return i; +} + static void intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, int link_bw) @@ -3578,6 +3605,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint8_t rev; if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, sizeof(intel_dp->dpcd)) < 0) @@ -3609,6 +3637,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) } else intel_dp->use_tps3 = false; + /* Intermediate frequency support */ + if (is_edp(intel_dp) && + (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && + (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && + (rev >= 0x03)) { /* eDp v1.4 or higher */ + intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_SUPPORTED_LINK_RATES, + intel_dp->supported_rates, + sizeof(intel_dp->supported_rates)); + } if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) return true; /* native DP sink */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1fb1529..1f41a83 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -626,6 +626,7 @@ struct intel_dp { uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; + __le16 supported_rates[DP_MAX_SUPPORTED_RATES]; struct drm_dp_aux aux; uint8_t train_set[4]; int panel_power_up_delay;