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[6/6] drm/i915/skl: Restore the DDI translation tables when enabling PW1

Message ID 1425667853-5717-7-git-send-email-damien.lespiau@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lespiau, Damien March 6, 2015, 6:50 p.m. UTC 
I was dumping the DDI translation tables to make sure my patch updating
the HDMI entry was doing the right thing when I noticed that the table
was showing reset values after DPMS.

And indeed, the DDI translation registers are in power well 1 on SKL,
and so we're losing their values when shutting down eDP.

Calling intel_prepare_ddi() on PW1 enabling re-programs the table.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Shuang He March 7, 2015, 1:32 a.m. UTC | #1 
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5908
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -13              275/275              262/275
ILK                                  307/307              307/307
SNB                 -1              284/284              283/284
IVB                                  375/375              375/375
BYT                                  294/294              294/294
HSW                                  385/385              385/385
BDW                 -1              314/314              313/314
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*PNV  igt_gem_exec_params_DR1-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_DR4-dirt      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_no-bsd      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-master      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_exec_params_secure-non-root      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_2-spare-fences      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-copy      PASS(2)      FAIL(1)PASS(1)
*PNV  igt_gem_fence_thrash_bo-write-verify-y      PASS(4)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_bad-flink      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_flink-lifetime      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_flink_race_flink_close      PASS(2)      NRUN(1)PASS(1)
*PNV  igt_gem_gtt_cpu_tlb      PASS(2)      NRUN(1)PASS(1)
*SNB  igt_gem_exec_params_rel-constants-invalid-rel-gen5      PASS(2)      DMESG_WARN(1)PASS(1)
*BDW  igt_gem_gtt_hog      PASS(5)      DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8d3bad8..ec3675e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -223,8 +223,10 @@  static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 						1 << PIPE_C | 1 << PIPE_B);
 	}
 
-	if (power_well->data == SKL_DISP_PW_1)
+	if (power_well->data == SKL_DISP_PW_1) {
+		intel_prepare_ddi(dev);
 		gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
+	}
 }
 
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,