| Message ID | 1426177893-17945-3-git-send-email-shobhit.kumar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 12, 2015 at 5:31 PM, Shobhit Kumar <shobhit.kumar@intel.com> wrote: > Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed > by display driver to enable the DSI panel on BYT platform where > the Panel EN/Disable control is routed thorugh CRC PMIC > > CC: Samuel Ortiz <sameo@linux.intel.com> > Cc: Linus Walleij <linus.walleij@linaro.org> > Cc: Alexandre Courbot <gnurou@gmail.com> > Cc: Thierry Reding <thierry.reding@gmail.com> > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> NACK. Spawn a separate MFD cell and write a fixed voltage regulator driver for this. > @@ -39,6 +39,7 @@ > #define GPIO0P0CTLI 0x33 > #define GPIO1P0CTLO 0x3b > #define GPIO1P0CTLI 0x43 > +#define GPIOPANELCTL 0x52 This is even a lie, you say in the commit message that the register is indeed named PANEL_EN/DISABLE and is not a GPIO. Yours, Linus Walleij
On Thu, Mar 12, 2015 at 5:31 PM, Shobhit Kumar <shobhit.kumar@intel.com> wrote: > Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed > by display driver to enable the DSI panel on BYT platform where > the Panel EN/Disable control is routed thorugh CRC PMIC > > CC: Samuel Ortiz <sameo@linux.intel.com> > Cc: Linus Walleij <linus.walleij@linaro.org> > Cc: Alexandre Courbot <gnurou@gmail.com> > Cc: Thierry Reding <thierry.reding@gmail.com> > Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> OK applied *this* version of the patch... Yours, Linus Walleij
diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c index 3d9e08f..91a7ffe 100644 --- a/drivers/gpio/gpio-crystalcove.c +++ b/drivers/gpio/gpio-crystalcove.c @@ -24,7 +24,7 @@ #include <linux/mfd/intel_soc_pmic.h> #define CRYSTALCOVE_GPIO_NUM 16 -#define CRYSTALCOVE_VGPIO_NUM 94 +#define CRYSTALCOVE_VGPIO_NUM 95 #define UPDATE_IRQ_TYPE BIT(0) #define UPDATE_IRQ_MASK BIT(1) @@ -39,6 +39,7 @@ #define GPIO0P0CTLI 0x33 #define GPIO1P0CTLO 0x3b #define GPIO1P0CTLI 0x43 +#define GPIOPANELCTL 0x52 #define CTLI_INTCNT_DIS (0) #define CTLI_INTCNT_NE (1 << 1) @@ -93,6 +94,10 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type) { int reg; + if (gpio == 94) { + return GPIOPANELCTL; + } + if (reg_type == CTRL_IN) { if (gpio < 8) reg = GPIO0P0CTLI;
Export PANEL_EN/DISABLE (offset 0x52) as additional GPIO. Needed by display driver to enable the DSI panel on BYT platform where the Panel EN/Disable control is routed thorugh CRC PMIC CC: Samuel Ortiz <sameo@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com> --- drivers/gpio/gpio-crystalcove.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)