From patchwork Mon Mar 16 15:58:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 6022521 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1A4569F314 for ; Mon, 16 Mar 2015 15:58:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 47AC5200DB for ; Mon, 16 Mar 2015 15:58:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 233982049C for ; Mon, 16 Mar 2015 15:58:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 212BB6E57F; Mon, 16 Mar 2015 08:58:17 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E450C6E57F for ; Mon, 16 Mar 2015 08:58:15 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 16 Mar 2015 08:56:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,410,1422950400"; d="scan'208";a="692846471" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.58]) by fmsmga002.fm.intel.com with ESMTP; 16 Mar 2015 08:58:14 -0700 Received: by rosetta (Postfix, from userid 1000) id 678F780057; Mon, 16 Mar 2015 17:58:13 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Mon, 16 Mar 2015 17:58:12 +0200 Message-Id: <1426521492-4315-1-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <87egoplyvy.fsf@gaia.fi.intel.com> References: <87egoplyvy.fsf@gaia.fi.intel.com> Subject: [Intel-gfx] [PATCH] drm/i915: Push mm switch immediately to ring X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sometimes when first batch is run with blitter ring, and even tho its PP_BASE has been properly set, the ring seems to be very confused about its memory view. The ring ACHTD keeps progressing past batch boundary, towards the end off address space. Eventually after quite amount of time, hangcheck will declare ring as hanged. But the proceeding reset can run into the same problem with the ring init. If we update the tail immediately after mm switch, the render ring will have a proper pd loaded, before the blitter ring is initialized. This fixes, or papers over, the blitter 'ACTHD proceeding through address space without progress' problem that has been quite a while in ppgtt=2 ring init. Also with Chris Wilson's patch to report GPU faults, I got page faults with unloaded PD's from address zero when running, igt/gem_ppgtt. This patch fixes also those. Testcase: igt/gem_ppgtt Testcase: igt/gem_reset_stats --r ban-blt Cc: Michel Thierry Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_gtt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 2034f7c..bbfcbb6 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -390,7 +390,7 @@ static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); intel_ring_emit(ring, (u32)(val)); - intel_ring_advance(ring); + __intel_ring_advance(ring); return 0; } @@ -896,7 +896,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); intel_ring_emit(ring, get_pd_offset(ppgtt)); intel_ring_emit(ring, MI_NOOP); - intel_ring_advance(ring); + __intel_ring_advance(ring); return 0; } @@ -931,7 +931,6 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); intel_ring_emit(ring, get_pd_offset(ppgtt)); intel_ring_emit(ring, MI_NOOP); - intel_ring_advance(ring); /* XXX: RCS is the only one to auto invalidate the TLBs? */ if (ring->id != RCS) { @@ -940,6 +939,8 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, return ret; } + __intel_ring_advance(ring); + return 0; }