From patchwork Tue Mar 17 09:39:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Imre Deak X-Patchwork-Id: 6029821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DF131BF90F for ; Tue, 17 Mar 2015 09:40:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0C5382045B for ; Tue, 17 Mar 2015 09:40:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 21F6D20035 for ; Tue, 17 Mar 2015 09:40:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4610D6E658; Tue, 17 Mar 2015 02:40:52 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 220936E656 for ; Tue, 17 Mar 2015 02:40:48 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 17 Mar 2015 02:40:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,415,1422950400"; d="scan'208,217";a="468316876" Received: from ideak-desk.fi.intel.com ([10.237.72.74]) by FMSMGA003.fm.intel.com with ESMTP; 17 Mar 2015 02:33:34 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Date: Tue, 17 Mar 2015 11:39:57 +0200 Message-Id: <1426585215-8788-32-git-send-email-imre.deak@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1426585215-8788-1-git-send-email-imre.deak@intel.com> References: <1426585215-8788-1-git-send-email-imre.deak@intel.com> Subject: [Intel-gfx] [PATCH 31/49] drm/i915/bxt: add description about the BXT PHYs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Extend the VLV/CHV DPIO (PHY) documentation with the BXT specifics. Signed-off-by: Imre Deak --- Documentation/DocBook/drm.tmpl | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7a45775..327757f 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -4067,7 +4067,7 @@ int num_ioctls; DPIO !Pdrivers/gpu/drm/i915/i915_reg.h DPIO - Dual channel PHY (VLV/CHV) + Dual channel PHY (VLV/CHV/BXT) @@ -4118,7 +4118,7 @@ int num_ioctls;
- Single channel PHY (CHV) + Single channel PHY (CHV/BXT) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a3579c0..95532b4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -718,7 +718,7 @@ enum skl_disp_power_wells { /** * DOC: DPIO * - * VLV and CHV have slightly peculiar display PHYs for driving DP/HDMI + * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI * ports. DPIO is the name given to such a display PHY. These PHYs * don't follow the standard programming model using direct MMIO * registers, and instead their registers must be accessed trough IOSF @@ -773,9 +773,13 @@ enum skl_disp_power_wells { * * Note: digital port B is DDI0, digital port C is DDI1, * digital port D is DDI2 + * + * On BXT the above mappings apply for both the dual and single channel PHY, + * with the difference that any of the three ports can connect to any of the + * three pipes. Also the single channel PHY is used for port A (DDI2/EDP). */ /* - * Dual channel PHY (VLV/CHV) + * Dual channel PHY (VLV/CHV/BXT) * --------------------------------- * | CH0 | CH1 | * | CMN/PLL/REF | CMN/PLL/REF | @@ -787,7 +791,7 @@ enum skl_disp_power_wells { * | DDI0 | DDI1 | DP/HDMI ports * --------------------------------- * - * Single channel PHY (CHV) + * Single channel PHY (CHV/BXT) * ----------------- * | CH0 | * | CMN/PLL/REF |