From patchwork Tue Mar 17 16:18:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 6032841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DD7DDBF90F for ; Tue, 17 Mar 2015 16:19:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 091A82035C for ; Tue, 17 Mar 2015 16:19:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 026632049E for ; Tue, 17 Mar 2015 16:19:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8A6526E732; Tue, 17 Mar 2015 09:19:12 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id CBB5A6E732 for ; Tue, 17 Mar 2015 09:19:10 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 17 Mar 2015 09:13:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,417,1422950400"; d="scan'208";a="699970391" Received: from rosetta.fi.intel.com (HELO rosetta) ([10.237.72.58]) by orsmga002.jf.intel.com with ESMTP; 17 Mar 2015 09:19:09 -0700 Received: by rosetta (Postfix, from userid 1000) id 43CDE80086; Tue, 17 Mar 2015 18:18:38 +0200 (EET) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Tue, 17 Mar 2015 18:18:36 +0200 Message-Id: <1426609117-11976-4-git-send-email-mika.kuoppala@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426609117-11976-1-git-send-email-mika.kuoppala@intel.com> References: <1426609117-11976-1-git-send-email-mika.kuoppala@intel.com> Cc: miku@iki.fi Subject: [Intel-gfx] [PATCH 3/4] drm/i915: Reorder hw init to avoid executing with invalid context/mm state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson Currently we initialise the rings, add the first context switch to the ring and execute our golden state then enable (aliasing or full) ppgtt. However, as we enable ppgtt using direct MMIO but load the PD using MI_LRI, we end up executing the context switch and golden render state with an invalid PD generating page faults. To solve this issue, first do the ppgtt PD setup, then set the default context and write the commands to run the render state into the ring, before we activate the ring. This allows us to be sure that the register state is valid before we begin execution. This was spotted when writing the seqno/request conversion, but only with the ERROR capture did I realise that it was a necessity now. RFC: cleanup the error handling in i915_gem_init_hw. v2: added intel_ring_reset v3: adapt to ring->start_ring Signed-off-by: Chris Wilson (v1) Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 8147e2e..5636351 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4856,11 +4856,25 @@ cleanup_render_ring: return ret; } +static int i915_gem_init_ring_hw(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_engine_cs *ring; + int i, ret; + + for_each_ring(ring, dev_priv, i) { + ret = ring->init_hw(ring); + if (ret) + return ret; + } + + return 0; +} + int i915_gem_init_hw(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *ring; int ret, i; if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) @@ -4898,13 +4912,7 @@ i915_gem_init_hw(struct drm_device *dev) */ init_unused_rings(dev); - for_each_ring(ring, dev_priv, i) { - ret = ring->init_hw(ring); - if (ret) - goto out; - } - - i915_gem_start_ringbuffers(dev); + i915_gem_init_ring_hw(dev); for (i = 0; i < NUM_L3_SLICES(dev); i++) i915_gem_l3_remap(&dev_priv->ring[RCS], i); @@ -4915,6 +4923,9 @@ i915_gem_init_hw(struct drm_device *dev) i915_gem_cleanup_ringbuffer(dev); } + for (i = 0; i < NUM_L3_SLICES(dev); i++) + i915_gem_l3_remap(&dev_priv->ring[RCS], i); + ret = i915_gem_context_enable(dev_priv); if (ret && ret != -EIO) { DRM_ERROR("Context enable failed %d\n", ret); @@ -4923,6 +4934,8 @@ i915_gem_init_hw(struct drm_device *dev) goto out; } + i915_gem_start_ringbuffers(dev); + out: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); return ret;