| Message ID | 1426672107-3076-5-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wednesday 18 March 2015 03:18 PM, Chris Wilson wrote: > Reuse the same reclocking strategy for Baytail as on its bigger brethren, > Sandybridge and Ivybridge. In particular, this makes the device quicker > to reclock (both up and down) though the tendency now is to downclock > more aggressively to compensate for the RPS boosts. > > v2: Rebase > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Deepak S <deepak.s@linux.intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 +++ > drivers/gpu/drm/i915/i915_irq.c | 4 ++-- > drivers/gpu/drm/i915/i915_reg.h | 2 -- > drivers/gpu/drm/i915/intel_pm.c | 7 ++++++- > 4 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index b156bc30c9c9..afb552c1a4f8 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1031,6 +1031,9 @@ struct intel_gen6_power_mgmt { > u8 rp0_freq; /* Non-overclocked max frequency. */ > u32 cz_freq; > > + u8 up_threshold; /* Current %busy required to uplock */ > + u8 down_threshold; /* Current %busy required to downclock */ > + > int last_adj; > enum { LOW_POWER, BETWEEN, HIGH_POWER } power; > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 6d8340d5a111..58af8e239971 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1050,7 +1050,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) > if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { > if (!vlv_c0_above(dev_priv, > &dev_priv->rps.down_ei, &now, > - VLV_RP_DOWN_EI_THRESHOLD)) > + dev_priv->rps.down_threshold)) > events |= GEN6_PM_RP_DOWN_THRESHOLD; > dev_priv->rps.down_ei = now; > } > @@ -1058,7 +1058,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) > if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { > if (vlv_c0_above(dev_priv, > &dev_priv->rps.up_ei, &now, > - VLV_RP_UP_EI_THRESHOLD)) > + dev_priv->rps.up_threshold)) > events |= GEN6_PM_RP_UP_THRESHOLD; > dev_priv->rps.up_ei = now; > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5b84ee686f99..c94c06b21052 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -671,8 +671,6 @@ enum skl_disp_power_wells { > #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 > > #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 > -#define VLV_RP_UP_EI_THRESHOLD 90 > -#define VLV_RP_DOWN_EI_THRESHOLD 70 > > /* vlv2 north clock has */ > #define CCK_FUSE_REG 0x8 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index e18f0fd22cf2..8b16bb3ae09f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3914,6 +3914,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) > GEN6_RP_DOWN_IDLE_AVG); > > dev_priv->rps.power = new_power; > + dev_priv->rps.up_threshold = threshold_up; > + dev_priv->rps.down_threshold = threshold_down; > dev_priv->rps.last_adj = 0; > } > > @@ -3985,8 +3987,10 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) > "Odd GPU freq value\n")) > val &= ~1; > > - if (val != dev_priv->rps.cur_freq) > + if (val != dev_priv->rps.cur_freq) { > vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); > + gen6_set_rps_thresholds(dev_priv, val); I think gen6_set_rps_thresholds should be under baytrail specific with platform check? > + } > > I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); > > @@ -4035,6 +4039,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) > & GENFREQSTATUS) == 0, 100)) > DRM_ERROR("timed out waiting for Punit\n"); > > + gen6_set_rps_thresholds(dev_priv, val); > vlv_force_gfx_clock(dev_priv, false); > > I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote: > >+ if (val != dev_priv->rps.cur_freq) { > > vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); > >+ gen6_set_rps_thresholds(dev_priv, val); > > I think gen6_set_rps_thresholds should be under baytrail specific with platform check? The only difference for cherryview is that it doesn't use GEN6_RP_MEDIA_TURBO. Was that intentional? The whole idea is that RPS should be autotuning for different workloads, but those metrics are equivalent across GPU. -Chris
On Wednesday 18 March 2015 04:53 PM, Chris Wilson wrote: > On Wed, Mar 18, 2015 at 04:45:08PM +0530, Deepak S wrote: >>> + if (val != dev_priv->rps.cur_freq) { >>> vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); >>> + gen6_set_rps_thresholds(dev_priv, val); >> I think gen6_set_rps_thresholds should be under baytrail specific with platform check? > The only difference for cherryview is that it doesn't use > GEN6_RP_MEDIA_TURBO. Was that intentional? > > The whole idea is that RPS should be autotuning for different workloads, > but those metrics are equivalent across GPU. > -Chris > Atleast based on the spec GEN6_RP_MEDIA_TURBO left out of CHV. I am yet to look at the latest Spec. Also, Most of RP register for CHV falls under Comman well, I hope re-adjusting the rps_threshold will not causing power issues since we have to wakeup both RENDER/MEDIA to access the register -Deepak
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b156bc30c9c9..afb552c1a4f8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1031,6 +1031,9 @@ struct intel_gen6_power_mgmt { u8 rp0_freq; /* Non-overclocked max frequency. */ u32 cz_freq; + u8 up_threshold; /* Current %busy required to uplock */ + u8 down_threshold; /* Current %busy required to downclock */ + int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6d8340d5a111..58af8e239971 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1050,7 +1050,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { if (!vlv_c0_above(dev_priv, &dev_priv->rps.down_ei, &now, - VLV_RP_DOWN_EI_THRESHOLD)) + dev_priv->rps.down_threshold)) events |= GEN6_PM_RP_DOWN_THRESHOLD; dev_priv->rps.down_ei = now; } @@ -1058,7 +1058,7 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { if (vlv_c0_above(dev_priv, &dev_priv->rps.up_ei, &now, - VLV_RP_UP_EI_THRESHOLD)) + dev_priv->rps.up_threshold)) events |= GEN6_PM_RP_UP_THRESHOLD; dev_priv->rps.up_ei = now; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b84ee686f99..c94c06b21052 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -671,8 +671,6 @@ enum skl_disp_power_wells { #define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000 #define VLV_CZ_CLOCK_TO_MILLI_SEC 100000 -#define VLV_RP_UP_EI_THRESHOLD 90 -#define VLV_RP_DOWN_EI_THRESHOLD 70 /* vlv2 north clock has */ #define CCK_FUSE_REG 0x8 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e18f0fd22cf2..8b16bb3ae09f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3914,6 +3914,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) GEN6_RP_DOWN_IDLE_AVG); dev_priv->rps.power = new_power; + dev_priv->rps.up_threshold = threshold_up; + dev_priv->rps.down_threshold = threshold_down; dev_priv->rps.last_adj = 0; } @@ -3985,8 +3987,10 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val) "Odd GPU freq value\n")) val &= ~1; - if (val != dev_priv->rps.cur_freq) + if (val != dev_priv->rps.cur_freq) { vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); + gen6_set_rps_thresholds(dev_priv, val); + } I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); @@ -4035,6 +4039,7 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) & GENFREQSTATUS) == 0, 100)) DRM_ERROR("timed out waiting for Punit\n"); + gen6_set_rps_thresholds(dev_priv, val); vlv_force_gfx_clock(dev_priv, false); I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
Reuse the same reclocking strategy for Baytail as on its bigger brethren, Sandybridge and Ivybridge. In particular, this makes the device quicker to reclock (both up and down) though the tendency now is to downclock more aggressively to compensate for the RPS boosts. v2: Rebase Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Deepak S <deepak.s@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_irq.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 -- drivers/gpu/drm/i915/intel_pm.c | 7 ++++++- 4 files changed, 11 insertions(+), 5 deletions(-)